Research And Implementation Of High Speed SerDes Phase-locked Loop And Pseudo-random Binary Sequence Generator For Satellite Laser Communication

High speed SerDes is the main transmission technology of the communication network.High-speed SerDes system for satellite laser communication equipment is based on the high speed SerDes technology of traditional communication equipment.In this paper a systematic architecture about high speed SerDes system is introduced and proposed.As a key module in high-speed SerDes system,the fractional-N phase locked loop is researched and designed.On the other hand,high speed transmission systems require high-speed signal sources for the verification,so this paper will introduce a high speed pseudo-random binary sequence generator and illustrate the design and implementation.This paper can be divided into three parts.The first part will introduce a high speed signal source used for high speed SerDes system verification.This high-speed signal source is a four-channel 23Gb/s pseudo-random binary sequence generator.This pseudo-random binary sequence generator is based on a 0.13?m SiGe BiCMOS process.The chip works under a 1.8V power source and consumes 198 mW.The second part of this paper is the high speed SerDes system applied to satellite laser communication technology equipment.Different from microwave wireless transmission technology,laser communication technology uses light as the signal carrier.At present,this technology is a new type of wireless transmission technology that many countries are actively researching.The high speed SerDes system designed in this paper will be used in this technology equipment.The data from the encoder and the decoder of the laser communication equipment are transmitted at higher speed and efficiency by high speed SerDes system.The main transmission data rate is 5Gb/s.The high speed SerDes system is designed based on the TSMC 55 G process,which is an improved version of the 65 nm one.The third part is to design a fractional-N phase locked loop module for high speed SerDes system.Because of the design requirements of the encoder/ decoder for satellite laser communication,the data rates and clock signals need to be divided into multiple fractional-N frequencies to make them work properly.Therefore,the most critical module in this high speed SerDes system is the phaselocked loop module.For this function of fractional-N frequency division,this paper proposes a method that can effectively apply the phase-locked loop to this high speed SerDes system and output four fractional-divided clocks.The clock signals are two 2.5 GHz,one 25/9 GHz and one 20/7 GHz frequency,respectively,and the power source is 1.8V.