Research Of Frequency Synthesizer And Transmitter In High Speed SerDes

Frequency synthesizer and transmitter are critical modules in high speed serial link,and how to generate high frequency,high performance clock with wide tuning range is the biggest challenge faced with the freqneucy synthesizer design,so as compensating the channel attenuation to the transmitter design.This paper shows the study of frequency synthesizer and transmitter.The basic principle of the frequency synthesizer is introduced briefly at the beginning,then a 10—12.5GHz LC phase-locked loop(PLL)is presented.This PLL adopts the following techniques to optimize the performance:(1)Utilize a fully differential structure to suppress the supply noise and the charge pump leakage noise.(2)Loop bandwidth is configurable to adjust the locking time and the phase noise.(3)A novel five-MOS switch capacitor structure is proposed,which has a higher Q value than the traditional three-MOS structure when the switch is open.The PLL is implemented in SMIC40nm CMOS technology,occupying a core area of 0.35×0.39mm~2.The measure result shows that under a 1.1V supply,the whole power dissipation is24.96mW.And the phase noise at 1MHz offset is-97dBc/Hz while the output frequency is 12.5GHz.Based on that PLL,a new PLL is designed,which introduces the following improvements:(1)Utilize two VCOs rather than one to better covering the wide frequency tuning range,and the VCO adopts the five-MOS switch capacitor,the indirect connecting varactor to enhance the Q value of the resonator,adopts the configurable tail current MOS structure to aviod the power waste.(2)An auto frequency calibration(AFC)circuit is introduced.This circuit uses an optimal control word storage algorithm based on binary search,which greatly shortens the calibration time and improves the band selection accuracy.(3)A lock detecting circuit is introduced to indicate the loop status.The new PLL is implemented in SMIC40nm CMOS technology,occupying a core area of 0.61×0.41mm~2.The post layout simulation result shows that under a 1.1V supply,the whole power dissipation is 19.85mW.And the reference spur suppression is-54.4dBc,the phase noise at 1MHz offset is-109dBc/Hz,the locking time is 5.5us with 4.4us is the AFC time,while the output frequency is 12.5GHz.Finally the design of the 10Gbps transmitter is introduced.First the channel and the equalization technique are studied,then the transmitter with FFE is introduced.The transmitter adopts the following techniques:(1)Use a half-rate structure to ease the strict timing constraint and simplify the design of high speed delay cell;(2)The high speed 2:1 serializer is implemented with transmission gate dynamic logic,so as to decrease the power dissipation;(3)A duty cycle correction circuit is introduced in the clock chain to optimize the clock quality,and some buffers are inserted on the chain to adjust the clock phase to guarantee the data sampling.The transmitter is implemented in SMIC40nm CMOS technology,occupying a core area of 0.14×0.2mm~2.The measure result shows that under a 1.1V supply,the whole power dissipation is 26mW.When the output data is 10Gbps PRBS-7 stream,the output eye presents a jitter of 57.17ps and an eye height of 180mW.