Design Of Frequency-locked Loop For 12.5GB/s SerDes CDR

Recent studies indicate that the input/output(I/O) bandwidth of serial links must increase by 2 to 3 times every two years in order to keep up with the demand for higher data rates. As one of the key components in SerDes systems, the clock and data recovery(CDR) limits the increase of the data rate directly. So the trend for pursuing higher speed CDR in SerDes systems has been demonstrated in the past and will continue in the future. For the PLL-based CDR, a high-speed clock is needed to sample the high-speed data flow. At the same time, the sampling clock needs to have low jitter, in order to improve the sampling precision. As a result, realizing the high-speed low-jitter clock is the important basic of the CDR system.In the project background of High-Speed Data Transmission, a frequency-locked loop is designed in this paper, which is a PLL circuit essentially. Three components of the PLL circuit is designed focally, so as to realize the high-speed and low-jitter characteristics of the output clock. Firstly, a cross-coupled delay cell without the tail current source is proposed. This structure can reduce the gain of the VCO and shift the control voltage into an appropriate range. Meanwhile, a precise bias circuit is not necessary without the tail current source, which reduce the complexity of the design. Secondly, a dynamic circuit of phase and frequency detector(PFD) is adopted, which can meet the need of the speed. Finally, a mirror-controlled charge pump with good performance in the low supply is designed to improve the jitter characteristic.Employing the 55-nm CMOS technology, the circuit and layout design of the frequency-locked loop has been completed with care. The supply voltage is 1.2V, and the outputs are rail-to-rail eight-phase clocks with the frequency of 3.125 GHz and the duty ratio of 47%. Moreover, the clock jitter is only 1.88 ps for pre-simulation and 5.85 ps for post-simulation. So the high-speed and low-jitter characteristics of the frequency-locked loop are achieved well.