Research And Design Of Full-rate Multipattern Pseudo-random Binary Sequence Generator In 40-nm CMOS

As the data rate rises up in high-speed broadband communication,the performance of these circuits is significantly higher than that of commercially available test equipment,so it brings a great challenge to chip the verification of chip function.In order to avoid the use of expensive test high-speed equipment and the channel loss of the cable between the device under test and the equipment at the high data rate.The currently widely used method is to directly generate input data for testing in a custom circuit inside the under device tested.This input data must be as close as possible to the real input signal.Pseudorandom binary sequence?PRBS?generators that can produce pseudo-random sequences have attracted much attention due to their inherent randomness and periodicity.Although the circuit structure of the PRBS generator is relatively simple,the main principle is to generate a specific sequence through a linear feedback shift register.It is challenging to realize a multi-pattern PRBS generator with low power consumption,small area,and high signal quality at a high output rate.The main research work of this thesis is as follows:?1?This work presents a compact low-power programmable multi-pattern pseudorandom binary sequence?MP-PRBS?generator.It is capable of producing 2⁷-1,2¹⁵-1,2²³-1 and 2³¹-1 test patterns to meet multiple testing requirements.?2?To reduce power and area,the full-rate architecture with the truly-single-phase clock logic?TSPC?D-flip-flops?DFF?instead of the current-mode logic?CML?DFF is adopted.The multiplexer?MUX?merged TSPC DFF is proposed to avoid the delay of the MUX in conventional multiple pattern PRBS generators.Hence,the critical path delay is reduced and thus the maximum data rate can be improved.?3?Fabricated in a 40-nm CMOS process,the digital logic circuit and analog circuit design,pre-simulation,layout design,post-simulation and chip testing were carried out under simulation software.The Altium Designer software is used to design PCB layout and simulate signal integrity.This PRBS occupies a core active area of 0.0037 mm2,and PCB area is 17.5 cm2.The chip operates at a maximum data rate of 15 Gb/s.The measured power consumption is 8.778 m W with 1.1-V supply.The figure-of-merit?Fo M?is 0.019 p J/bit at the pattern length of 2³¹-1.The jitter of the output waveform is 23.36 ps.