Research On The Key Technology Of High Efficiency And High Speed Phase Locked Loop

With the development of the chip industry,the demand for microprocessor performance has become higher and higher,and the design level of microprocessors has also entered the era of high-speed development.In the process of continuous upgrading of technology and manufacturing technology,the size of the process becomes smaller and smaller,and the ability of microprocessors is also developing with the level of design technology.As a result,the processing speed is faster and faster,but the power consumption is getting lower and lower.The Phase Locked Loops(PLL)can make the frequency synthesis of the low-speed low frequency clock input to the external input,and provide the high-speed clock for the microprocessor.In this theory,the phase error of the charge pump phase locked loop(CPPLL)can be zero,and in practical application,it also has the advantages of high speed,low power consumption and low jitter.It is very important in practical application.Therefore,it is very appropriate to design a high efficiency and high speed phase locked loop and select the charge pump lock phase ring.Large scale integrated circuit technology has very mature technology in the present era.CMOS technology has many advantages,such as low cost,low power consumption,high integration,strong anti-interference ability and so on.It is widely used in current circuit design.At the same time,CMOS technology is becoming more and more irreplaceable in today's design and manufacturing.One of the technological manufacturing technologies that have been developed in the future.Therefore,designing an efficient and high-speed CMOS phase-locked loop has a very practical application value.In the first chapter,we introduce the development and background of phase-locked loop,and then analyze the structure and the basic principle of PLL.Secondly,we introduce the effects and solutions that will affect the circuit performance in the process of circuit design.Then,based on the linear time invariant model,the function of the noise source of each module of the PLL is derived.Based on this,the noise is optimized from the design point of view.After the theoretical analysis of the system,the five basic modules of the phase locked loop are deeply analyzed and studied.For the PFD circuit,the phase dead zone is reduced by increasing the delay.The charge pump circuit uses a differential structure to improve the charge and discharge matching degree of the charge pump;the phase locked loop circuit selects the three order loop.The filter,which can effectively suppress the high frequency noise of the circuit,is designed for the LC PLL circuit,the voltage controlled oscillator is a capacitive inductance VCO,and the structure of VCO has better noise.In this thesis,the principle of the most basic phase locked loop is analyzed.By combining the theory with the actual design and optimizing the adverse factors in the circuit,a high efficiency and high speed phase locked loop is designed.The main analysis of how to reduce the influence of the parasitic capacitance and how to reduce the sound and noise optimization circuit are discussed and studied systematically.The.The whole phase locked loop ultimately meets the specific parameters set by the application.Based on the technology of SMIC0.18 ?m,a LC charge pump phase locked loop circuit is designed in this thesis.The chip power supply voltage 1.8V,input reference frequency 10 MHz,frequency locking range from 5.1GHz to 5.4GHz;in the range of working frequency of the chip,the loop lock time is not more than 60 ?s charge pump PLL circuit.