Design And Implementation Of Bulit In Self Test Circuit For SRAM Memory Array

In recent years,with the rapid development of large scale integrated circuits,the design scale of SOC(System On Chip)circuits has been increasing and design cycle have become longer.In order to improve design efficiency,some standard circuitsare designed as IP(Intellectual Property)cores.Then,the SOC circuits can be bulit quickly through the IP multiplexing technology,in order to reduce the circuit design difficulty and shorten the design cycle greatly.Embedded memory IP,as a module for data storage and exchange,has advantages such as high speed and high density.However,it may potentially cause high failure rate.This disadvantage will become a huge obstacle to the further development of SOC.There are two main types of embedded memory IP design methods including full-custom design and memory compiler generation.There are two different methods to test the two IPs.To test the first one,designers only need to test the specific memory,while testing the second one,designers often need to use the compiler to sample different types of memory and build a memory array.The evaluation of the memory compiler is achieved by testing the memory array.The advantages of memory built in self test(MBIST)are as follows:high fault coverage,low test equipment dependency and low test complexity.Hence MBIST is favored by many companies.This paper takes MBIST as the core and introduces a SRAM(Static Radom Access Memory)Compiler test circuit which includes both storage fault and timing parameter measurement.Firstly,in accordance to the research background and development status of memory test,this paper summarizes the common defect types and test algorithms in memory test.Meanwhile,it discusses the structural characteristics of SRAM Compiler and MBIST memory functional test circuit,which is based on a hybrid test algorithm.Then the paper proposes a new memory timing test method which is based on the functional test circuit and the actual demand.To present the method,the storage unit data read time has been tested as an example.Finally,the completed MBIST circuit is physically manufactured.We verify its functionality by testing the chip.In this paper,the MBIST test circuit is manufactured by UMC 28nm CMOS process.It mainly studies the fault test of SRAM Compiler and evaluates the compiler by sample testing.We have tested and verified the chip successfully.Compared with the traditional BIST circuit,the MBSIT circuit can be used for the memory array function and reading time in memory test and the test speed remaining unchanged and the chip area only increasing by 1.31 ‰.