Reducing test data volume for system-on-chip integrated circuits using test data compression and built-in self-test

Ever-increasing circuit densities and the use of system-on-chip (SOC) designs have resulted in enormous test data volume for today's integrated circuits. Higher test data volume not only leads to increased testing time, but it may also exceed the available memory depth on the channels of automatic test equipment (ATE). Therefore, new techniques are needed for reducing test data volume and test application time, thereby reducing test cost.; This thesis presents a set of new techniques to mitigate the SOC testing problems resulting from the dramatic increase in test data volume. These techniques are based on data compression algorithms, alternative scan architectures, built-in self-test, and a combination of these approaches.; The first contribution of this thesis lies in the use of exponential-Golomb codes and subexponential codes for the compression of scan test data in core-based SOCs. Analytical characterization and experimental results show that these codes often provide greater compression than alternative methods that have been proposed recently. The decoding logic for these codes can be easily implemented in hardware for efficient on-chip decompression.; The thesis next presents test data compression using dictionaries with selective entries and fixed-length indices. The dictionary-based approach not only reduces testing time but it also eliminates the need for additional synchronization and handshaking between the SOC and the ATE. The dictionary entries are determined during the compression procedure by solving a variant of the well-known clique partitioning problem from graph theory. Experimental results for benchmark circuits and representative test data from IBM show that the proposed method outperforms a number of recently-proposed test data compression techniques. Compared to the previously-proposed test data compression approach based on selective Huffman coding with variable-length indices, the proposed approach provides higher compression for the same amount of hardware overhead.; A technique based on alternative scan architecture is next presented. A gated fan-out structure is used to expand the narrow input data stream from a small number of ATE channels into a wide output data stream to drive a large number of internal scan chains. This approach achieves up to ten times reduction in scan test data, volume and testing time with negligible on-chip hardware overhead. (Abstract shortened by UMI.)...