Design And Implementation Of Test Circuits Based On Embedded SRAM

With the continuous development of integrated circuit technology,the scale density of circuit integration is gradually increasing,and the increase in density will inevitably bring the possibility of failure,so the test ability design in the chip design process is particularly important.The proportion of memory in the chip is increasing year by year,to a certain extent,whether the memory can operate normally is a necessary condition for the success of the chip,how to test the memory is an important content of people’s research,memory built-in self-test is an important area in test ability design,by writing the test algorithm into the chip,the chip self-generated test vector is realized,getting rid of the dependence on expensive equipment.With the continuous development of process technology,people have discovered a variety of hidden fault types,this thesis will improve the test algorithm based on the static failure model and optimize the test structure.The research content of this thesis is as follows:(1)An improved March LR algorithm is proposed,and a general test algorithm improvement process is provided.March LR algorithm has better detection ability,but for static fault single unit fault and two unit coupling fault detection ability is insufficient,for the fault types that March LR algorithm cannot cover,an improved algorithm process is proposed to improve the March LR algorithm,and the coverage of the improved March LR algorithm on static faults is nearly 35.8% higher than that of the original March LR algorithm.(2)A counter-based double-layer state machine test structure is proposed.Chips often contain multiple types of memory,and the inconsistency of multiple types of memory ports generally requires the design of multiple test structures,and the difference in data and address also brings challenges to memory testing.Aiming at the test structure problem of multi-type memory,this thesis proposes a counter-based double-layer state machine test structure,the top-level state machine controls the order of the test memory,the algorithm state machine module controls the operation of the algorithm,the counter module provides state transfer conditions for the algorithm state machine module,and provides the generation of address,the control module cuts the address and write read port according to the memory valid state of the top-level state machine,and the design structure can test different types and sizes of memory at the same time.(3)This thesis uses the integrated circuit design process of 55 nm process to complete the circuit structure design,the circuit design can test a wide range of memory of different sizes,after a complete front-end and back-end design,the functional simulation results are normal,the final layout meets the design rule check,circuit matching rules,etc.,and finally the design layout is submitted to the manufacturer for actual tape-out testing.