Research On Built-in-self-test Of Memory-blocks In FPGAs Based On Minimizing Configurations

As the continous development and the expanding application area of FieldProgrammable Gate Array (FPGA), the Memory-Blocks has become indispensablecomponents in FPGA to satisfy large capacity and high bandwidth data storage requirementin various application. Memory-Blocks-testing is one of the biggest challenges of FPGAmanufacture testing, as the quantity and the scale of the Memory-Blocks in FPGA arerapidly increasing, especially as the appearance of assistant logic hardware. How toeffectively complete manufacture test of Memory-Blocks, Therefore, has important realisticmeanings for reducing the cost and development of FPGA.The difficulties of testing Memory-Blocks in FPGA mainly include how to choose thetest-configuration, which algorithm is perfect for every test-configuration and how torealize the algorithm to perform the test process.Addressing the configurability of Memory-Block, a universal test configurationminimization approach was proposed. By investigating the realization mechanism of allmodes of Memory-Block to determine the fault covers of each configuration and theneliminate the redundant configurations to minimize the number of test configurations,finally select necessary algorithms to test simple-fault, linked-fault and dual-port fault mayexist in Memory-Block.Build BIST architecture using own hardware resource in FPGA to implement the testprocess. Because of the portability of Verilog HDL, The BIST architecture, designed byVerilog, can be easily reused for different Memory-Block in different FPGAs. Simulated byModelsim and performed in real FPGA chip, prove the correctness of BIST architecture.Addressing the numerous quantities of Memory-Blocks, several Memory-Blocks usingjust one TPG was adopted to realize concurrent test of Memory-Blocks. This measure helpsdecrease the usage of hardware resource in FPGA and reduce test power dissipation. Bymeans of comparing output of one Memory-Block with each other’s, no need to providereference data by TPG, this measure also helps reduce the design difficulty of TPG.The experiment results demonstrate the proposed approach remarkably decrease thenumber of test configurations thereby saving the entire test time, furthermore, comparedwith the existing approach, proposed approach has higher fault coverage and is moreuniversal.