Design And Test Of SRAM IP At Speed Test System

As IC feature size decreases and operating frequency improves continuously, memory failure is no longer a simple function failure. The performance failures caused by slight delay of the circuit are counted in IC design and test. This thesis mainly works at the research and design of static random access memory (SRAM) at-speed test chip which takes the built-in self test as a basic technique.SRAM at-speed test mainly includes function test and performance test. As to functional test, this paper firstly analyzes the memory common type of fault and studies several popular memory test algorithms, then puts forward a novel test pattern that can effectively detect the failures such as coupling failure and neighborhood pattern sensitive failure, which can not be detected using conventional March C algorithm. Based on the new test algorithm and the up-down design rule, the BIST system is designed and simulated. The simulation result indicates that it can go through the whole failure detection at high speed in multiple data background with a higher failure coverage and a faster test speed.For the performance test, this paper uses at-speed technique by expanding the BIST system with an ADPLL and clock delay chains. The ADPLL generates high frequency clock and the delay chain produces4-phase clock. The offset between the4-phase clocks are used as the performance parameters. By tuning the external delay option pins, ADPLL generates varied frequency. These varied frequencies provide engineers an intimate SRAM IP operating environment, in which the performance failures caused by subtile delay can be easily detected. This thesis presents an exhaustive account of principles and test process to measure the SRAM performance parameters with the at-speed test chip. Finally the measured values are compared with the pre-simulated values.The designed chip is tested at25℃employing TT process corner with operating frequency from400MHz to the value used in pre-simulation. The at-speed test chip is taped out with55nm SPRVT1P10M low-K process, and delivered to customer for SPRF SRAM IP test. The package type is QFP100.