Research And Implementation Of Digital Calibration Technology For SAR ADC

Analog-to-Digital Converter(ADC)is an indispensable interface module for converting continuous analog signals into discrete digital signals.There are many types of ADCs,However,Successive Approximation Rigister(SAR)ADC is unique in portable consumer because of its simple structure,small area,low power consumption and more suitable for the continuous evolution of advanced processes.Electronics,medical device equipment,industrial control,and digital acquisition have received widespread attention and application.In the above application fields,higher requirements are placed on the performance of SAR ADCs.At the same time,with the continuous evolution of nano-scale CMOS technology,the design of high performance analog circuits is becoming more and more difficult,and digital calibration technology has been widely used to assist in the realization of high performance ADCs.Based on the existing research,firstly,the non-ideal factors of SAR ADC are analyzed,such as parasitic capacitance,capacitance mismatch and other effects.Then,the digital calibration techniques of SAR ADCs with different implementation methods are summarized,and their advantages and disadvantages are analyzed.Through analysis,this paper studies two digital calibration schemes to help achieve high performance SAR ADC.The specific research contents include:First,a 12-bit 1MS/s foreground digital self-calibration SAR ADC is studied.The algorithm for calibrating DAC and compensating calibration code is improved.A series three-segment 7 bit calibration DAC array structure is proposed to calibrate the high 6-bit error voltage.The proposed structure to achieve the purpose of reducing the area and expanding the calibration range.Meanwhile,Calibration logic control process is also simplified by setting the initial state of the calibration DAC as the intermediate state.In addition,the "double registers" pre-judgment method is adopted to improve the efficiency of the compensation of the calibration code.Design and reception digital implementation of self-calibration of SAR ADC in 110 nm CMOS technology,the simulation results show that SNDR is improved from 49 dB to 71.1 dB.DNL is reduced from-1/+21.250 LSB to-0.25/+0.5 LSB.INL is reduced from-17.398/+10.152 LSB to-1.048/+0.792 LSB.Secondly,a 14-bit 30MS/s background digital calibration SAR ADC based on disturbance signal injection is studied.The calibration algorithm can detect calibration in real-time in the background and has a large tolerance limit for capacitor mismatch.Firstly,the digital calibratability of DAC capacitance mismatch is introduced.Then the relationship between weight coefficient,quantization number and error tolerance is analyzed,and the appropriate combination is selected.The background digitally calibrated SAR ADC based on disturbance injection is used to model the behavior of the entire calibration system through the Simulink platform.The simulation results show that SNDR is improved from 52.9 dB to 83.4 dB.DNL is reduced from-0.88/+1.3 LSB to-0.9/+0.92 LSB.INL is reduced from-13/+14 LSB to-1.2/+1.3 LSB.