AMOLED Display Driver Chip Mipi Interface Protocol Design

With the increasing development of mobile electronic products,the importance of screen display effects in electronic products has become more and more prominent.AMOLED screens have developed rapidly due to their good display effects,low power consumption,and thinness,and have become the mainstream display panels for current electronic devices.However,due to the increase in screen size and the increase in refresh rate,huge challenges are presented to the transmission performance and transmission power consumption of the AMOLED screen display driver chip data interface.How to improve the transmission rate of the AMOLED screen display driver chip interface and reduce the transmission power consumption has become an important issue for the research and development of AMOLED display driver chips.This paper studies the two different MIPI transmission mechanisms in MIPI D-PHY protocol and MIPI C-PHY protocol,analyzes the theoretical transmission rate of the two transmission mechanisms,and compares MIPI C-PHY protocol as the design basis of the interface circuit.Further study the MIPI DSI-2 protocol,analyze and extract the specific functions of each layer of the MIPI interface,and determine the working mode of the MIPI interface.This article adopts the basic architecture of AMOLED screen driver chip.Based on this architecture,an interface protocol circuit based on the characteristics of the C-PHY physical layer is designed,and the Verilog HDL hardware description language is used for RTL-level code design and implementation.In order to solve the problem of insufficient high-speed clock recovery at the end of the transmission of each channel of the C-PHY physical layer,this paper adopts the method of clock domain conversion to advance the channel management layer,protocol layer and application layer circuits to the internal clock domain of the drive chip system.The situation of untimely data processing is eliminated;compared with the method of directly supplementing the tail clock,this method saves clock power consumption and area.At the same time,the interface data is reduced in frequency to improve the stability of high-speed transmission,and solve the handshaking timing problem caused by the increase in transmission rate.The swap switch module is designed to adjust the physical wiring sequence inside the interface circuit,which solves the situation that the transmission data error occurs after the interface channel is misplaced during packaging,and further improves the compatibility of the circuit.This article is to verify whether the designed interface circuit meets expectations.First,use shell and perl scripting language to build a simulation platform that can automatically compare interface input data and output data;in this platform,VCS software is used for functional simulation,Verdi software is used for circuit waveform inspection,and n Lint software is used for code semantic inspection and Optimization,the simulation platform results show that the comparison accuracy rate reaches 100%,which verifies the correct functionality.Secondly,the UMC40 nm process library is used to synthesize the design circuit through the Design Compiler synthesis tool;the final report shows that the design circuit area is 61752.21?m2,the power consumption is 166.99 m W,and the area is reduced by 10% compared with the D-PHY physical layer interface protocol circuit.,The power consumption is reduced by 8%.In addition,the circuit is analyzed by the Prime Time timing analysis tool;the transmission rate can reach 2.5Gbps,which can support higher resolution and higher screen compared with the transmission rate of the interface circuit of the D-PHY physical layer of 1.5Gbps.Refresh rate.Based on these three verification results,it is judged that the designed interface circuit has reached expectations.The design of the entire interface circuit provides an interface protocol circuit design idea based on the characteristics of the C-PHY physical layer for the display driver chip industry.