Research On Time Doman Method And Circuit For Quantization Noise Optimization Of Fractional-N Phase-Locked Loop

Nowadays,digitization gradually covers every corner of the world.The development of 5G accelerates this efficient application mode,which requires higher speed and accuracy of terminal processing information.As the source of clock generation,PLL need output signals with high resolution,strong stability and low phase noise to improve the performance of the system.As a flexible and high-resolution technology,fractional frequency division is widely used in PLL.Quantization noise caused by the "average" period difference of Delta-Sigma fractional frequency division has become a technical bottleneck for high-performance PLL to break through.It is a hot and difficult point in the international research of fractional-N PLL in recent years.The quantization noise suppression technology which has not been widely involved in China.In this paper,the aim is to design a digital circuit with high resolution,simple structure and it can optimize the quantization noise of the fractional-N PLL.Firstly,this paper introduces the principle of fractional frequency division phase-locked loop and the characteristics of each circuit module in phase-locked loop,and establishes the loop linear model and noise model in theory.The quantized noise shaping effect of modulation technology in fractional frequency division phase locked loop is analyzed.The noise suppression ability of modulator with different order and its own noise influence are calculated.By comparing several optimization techniques of quantized noise in the world,their advantages and disadvantages are analyzed.Then,according to the theoretical analysis results,in Simulink,the fractional frequency division PLL is modeled and simulated,and the loop characteristics of PLL and the function of modulator are analyzed from the model.It can be seen from the simulation waveform that modulator quantization will introduce new noise into PLL.The noise effects caused by signals with different phase jitter difference from reference signal are modeled and calculated in Matab.A time-domain compensation method of quantized noise is proposed through comparison.In this paper,a quantized noise optimization circuit is designed based on the time domain compensation method.The design method of combining modulator,DTC and multi-mode frequency divider is adopted.The delta-sigma modulator controls the multi-mode frequency divider to produce different frequency division ratios and adjusts the corresponding time interval of DTC to keep the output signal cycle as consistent as possible.In addition,the DTC designed in this paper uses a new idea.The coarse tuning of DTC is designed by phase interpolation of inverters.The fine tuning of DTC constitutes a Miller capacitor by triggering the Miller effect of inverters.The whole design uses standard cells and it is a digital circuit.According to the principle of phase interpolation,another digital circuit DCO designs for providing oscillation signal in simulation.In addition to the above two circuit designs,there are also digital circuit design modules of multi-mode frequency divider(MMD)and modulator.Based on 40 nm CMOS technology,a digital quantization noise optimization circuit of fractional-N phase locked loop is presented in this paper.At 1.1V voltage,The tuning range of 9-bit DTC is 115.5ps,the resolution is 251 fs,the INL is 1.35 ps,the DNL is 121 fs,and the power consumption is 3.5m W.Delta-Sigma modulator and multi-mode divider use as fractional frequency division of the loop.The compensation technology of DTC suppresses the noise caused by quantization.