Research Of Time-to-Digital Converter And Counter For All Digital Phase Locked Loop

Nowadays, more and more wireless communications standards keep emerging. Therefore, the Time-to-Digital Converter (TDC) and All Digital Phase Locked Loop (ADPLL) become attractive research topics both in industry and academic. In general, this thesis describes the TDC and counter for ADPLL, integrated with other modules and finally the synthesizer is implemented in CMOS technology.This thesis firstly discusses the architecture of ADPLL and proposes the phase measurement schemes. Then, the architecture analysis and index analysis are proposed. My design scheme is also proposed.A two-stages TDC is proposed in this work. The1st stage uses buffer delay chain for the coarse quantization while the2nd stage uses Vernier delay line for the fine quantization. It avoids the bad linearity without the long chain and achieves the high resolution by the2nd stage.About the inner stage of the two-stages TDC, an innovative residue selection circuit is proposed, which records the residue between the reference signal and the nearest delayed data signal. It includes selection signal generator and two same multiplexers. And it theoretically introduces zero nonlinear deviation and linear offset.The following optimized TDC design departs period measurement and interval measurement. Interval measurement uint samples the edge of the high frequency signal, and simplifes the design with the better linearity and less area and power.A counter for high-frequency wideband signal and sampling circuit applied in different timing domain are proposed. The sampling circuit includes retiming clock generator, which generates the retiming clock synchronized with the high frequency data signal by oversampling, and sampling part based on the clock tree design corresponding to the data results. It is one practicable scheme for the low-frequency clock to sample the high-frequency data.The TDC and counter applied in ADPLL are designed in0.13μm CMOS technology, which run at1.2GHz-2.6GHz high-frequency data signal from a40MHz reference signal with simulation verification. TDC achieves8.5ps resolution by test. TDC and counter occupis0.26mm2.