The Research And Implementation Of 12-bit SAR ADC Based On C-R Architecture

As a key component of interface between analog system and digital system,analog-to-digital converter(ADC)has been widely used in various micro-control units(MCU).It integrates internal processor,counter,memory(FLASH?ROM),serial communication(I2C?SPI?UART),analog module(ADC?CLOCK?LDO),and I/O ports.In recent years,the Successive Approximation Register(SAR)ADC is especially suitable for MCUs with low speed requirements but low power consumption and medium and high accuracy,because of its comprehensive advantages such as low power consumption,high accuracy and small area.Based on the systematic analysis of SAR ADC,a 12-bit SAR ADC based on hybrid capacitance-resistance architecture is developed.The circuit design of the chip is completed and successfully integrated into a general MCU.Finally,the chip is streamed and tested.The main innovations of this design are as follows:(1)Around the compromise of low power consumption,high precision and low cost,this design adopts hybrid capacitor resistance(C-R)ADC structure.The most Significant Bit(MSB)is scaled by charge,while the Least Significant Bit(LSB)is scaled by voltage.In the design of high-bit capacitance,thermometer coding and binary decoding are used,and the symmetrical structure of common centroid is adopted in the layout,which can effectively suppress parasitic capacitance,device mismatch and signal crosstalk.The low-position resistor series voltage divider adopts only one resistor series,which effectively reduces the generation of power consumption.In this module,a new method to improve DAC conversion accuracy in SAR ADC is proposed,which makes DAC network have more accurate sampling performance.(2)Considering that the accuracy,speed and power consumption of the comparator have an important impact on the performance of the whole A/D converter,this design adopts a pre-amplified latch comparator design,which consists of four parts cascaded:bias start circuit,folded cascode operational amplifier circuit,Latch comparator and RS flip-flop output stage.Folding cascode operational amplifier circuit is the core part of the comparator.Its advantage is that it can not only improve the power supply voltage noise suppression ability,improve the gain,but also no static power generation.(3)In the design and implementation of SAR logic circuit,aiming at the problems of complex design,high power consumption and many circuit nodes of traditional SAR logic structure,a new serial SAR unit structure is proposed to generate shift register sequence and record quantization results.The new SAR logic ensures the stability of the system and has good linearity.The chip is realized by Magna 0.13 um CMOS technology.The ADC layout area is only 0.092 mm~2,and the working voltage can be 3.0V~5V.The simulation results show that the differential nonlinearity(DNL)of the chip is-0.43/+0.335LSB,the integral nonlinearity(INL)is-0.78/+0.6LSB,the spurious dynamic range(SFDR)is84dB,the signal-to-noise distortion ratio(SNDR)is 65.5dB,and the effective bit is10.6bit.The chip test results show that the ADC function is normal,the integral nonlinearity(INL)is-1.5/4.5LSB,the input sampling frequency of ADC is 62.5KHz,and the power consumption is 0.9mW when the working voltage is 3V,which meets the requirements of mass production.