Design Of High Successive Approximation ADC Applied In Micro-accelerator

Nowadays, analog-to-digital convertor(ADC) are widely used in the field ofindustry and military as a bridge between the analog-circuit and digital-circuit.Among all ADC types the over-sampling ADC has the highest resolution, and theparallel-ADC has the fastest rate of comparing, while the successive approximationADC takes compromise of speed and resolution with the advantages of low powerconsumption and low cost. A successive approximation ADC is designed which isintended to use in the capacitor self-calibration model of the interface circuit ofmicro-accelerometer. The dissertation begins with the principle of operation, thendepicts the design of core part of the circuit, finally, the simulation of the core partand the whole system is given.The12-bit successive approximation ADC in this dissertation is under0.5umCMOS process, which has the sampling frequency of250KS/s with the range of inputsignal0-5V and a power supply of5V. A charge calibration architec ture is used toimprove the resolution, and a segmented capacitor reduces the total capacitance of thecapacitor array, thus the power consumption and area is reduced effectively. Ancascaded latch comparator with pre-amplifier is to achieve a high resolution and highspeed comparator. The comparing resolution of the comparator is enhanced byadopting the error-calibration technique that can decrease the offset voltage of thecomparator. The digital control circuit adopts the full-custom transistor-level design,which has small quantities flip-flops with the system power consumption reducing.According to the result of simulation, the SNR of successive approximation ADCin this dissertation reaches69.8dB, while the SNDR is66.9dB, the ENOB is10.8bitsand the system consumption is8.01mW.