Research And Design Of A12Bit CMOS Fully Differential SAR ADC

As system-on-a-chip (SoC, System on Chip) and the rapid development of digital processing technology, especially the development of the microcontroller (MCU),digital signal processor (DSP) and the micro mechanical electronic systems (MEMS). Using digital circuit to deal with analog signal becomes the inevitable trend of the development of large scale integrated circuit, and it also makes the analog-to-digital converter (ADC) become more important. ADC mainly adopts the structure of Σ-Δ, Pipeline, folding type, a full parallel flashing type (flash), the two step type and successive approximation (SAR). The circuit principle of SAR ADC is relatively simple, and due to the medium speed, the moderate resolution and the low power consumption, SAR ADC is widely used in embedded systems such as sensor networks, medical equipment, and industrial measurement.Based on TSMC0.18μm1.8V/3.3V CMOS process, a1MSps differential SAR ADC which adopts the differential resistance capacity hybrid structure is designed in this paper. A new DAC_SUB of resistance and time self-adjusting comparison are put forward, and the influence of the VCM jitter on the circuit is calculated. The whole differential resistance capacity hybrid structure DAC_SUB using capacitance in high8bits, and using resistance in low4bits. While guarantee the accuracy, it can save area maximally. The device occupied a layout area of390um x780um, test results show that under1Ms/s sampling rate, when the input signal frequency of31.37kHz, the ENOB10.76Bit ADC, and the power consumption is about2mW.