The Study And Design Of Dual-Path Phase-Locked Loop For PCI-Express 2.0

High speed serial interface has gradually replaced the conventional parallel interface for the characteristics of easy connection,high speed and low hardware.The circuit of high speed serial interface is composed of transmitter and receiver,and both serial and deserialize need phase-locked loop(PLL)circuit.In this dissertation,a high speed PLL was designed,which was used in PCI-Express 2.0.The dissertation paid more attention on the research of theory of PLL,noise analysis,circuits and layout.The main work and achievements are presented as follows: 1)Due to the problems of small frequency tuning range and large gain of the voltage-controlled oscillator(VCO)caused by low power supply,a high speed single-input dual-path PLL which implemented coarse and fine has been proposed for PCI-Express 2.0,coarse loop guaranteed large frequency coverage area,fine loop reduced the gain of VCO.At the same time to reduce power consumption and chip area,the VCO used a ring structure to replace the traditional LC structure,which reduce power consumption and chip area on condition that prefermance.2)The PLL theory as the noise contribution of each module was deeply analyzed,and a scheme was put forward by verifying the theory through Verilog-A,and the tradeoff between loop filter,bandwidth,phase margin,charge pump current,VCO gain(Kvco)and frequency ratio were verified.3)A novel lock detection circuit was designed,the method was used the reference clock and feedback clock mutual sampling.The characters of this circuit were not only small chip area,power consumption but also prevent false locking.4)To compatible with high speed and low speed mode of PCI-,Express 2.0,the output frequency can switch freely at 1.25 GHz and 2.50 GHz,and does not affect the stability of the loop.In order to test,various unity gain bandwidths were designed at 1.25 GHz and 2.50 GHz by programming.5)After completed the full chip design,and according to the mixed signal design rule,the layout of PLL circuit was designed,and the post-layout simulation was accomplished.The circuit and layout were designed in SMIC 55 nm 1P8M CMOS process.Thefull chip area including IO pad and testing module is 1.495 mm2,and the active area is only 0.152mm2.Pre simulation results showed that the phase noise of the VCO was-98.2dBc/Hz,-99.3dBc/Hz@1MHz offset when the output frequency were locked at 2.50 GHz and 1.25 GHz,and post simulation results showed that the maximum jitter of control voltage were 0.33 mV and 0.12 mV,respectively.The supply voltage is 2.5V and 1.2V,the maximum power consumption is when it is locked at 2.50 GHz and 1.25 GHz,the maximum power consumption is 15.6mW and9.6mW,respectively.