To Achieve The Level Of Back-end Of The Asic Chip

Based on the back end design of a test chip, the dissertation studies the key technology in a hierarchy place and route flow and some solutions on how to improve chip performance during the implantation. The test chip is a SOC design with ZSP core, and it had been taped out in IBM and passed all system level testing.In a complex chip , how to hierarchical the design depend on the function, and the target is each level can concurrent plan then implement, and at the same time must take the relation ship between two levels into account, and also the internal design of a level. When full chip floor plan is going on, the set up of boundary timing constraint and place and interface design are all very important. For power plan must reduce the effect of IR drop and electron migration. As the key part of a timing driven design, clock tree synthesis and optimization is very special in a hierachical design and tool should calculate the actual clock network delays after the clock tree is built instead of using ideal clock. When the timing closure is done in place and CTS stage, we will do timing driven route. In the process of deep sub-macro, signal integration become more import besides timing for a IC design, and as one of effect element the cross talk is the most serious issue after route the design. Static timing analysis is very quick and effective on timing check, it can report almost all timing violations. In order to reduce the complexity and save runtime, we can do sub module STA first then full chip. For a routed design, we can update the design function or timing by doing engineering change order. It is a good way to save cost and runtime.A complete flow play an import role in back end design of a chip, but it still need updated and improved, and at the same time take more skills on improving performance then we can be successful in more complex design and advanced manufacture process.