Research On Clock Tree And Power Consumption Optimization Of MCU Control Chip Based On 0.13μm Proces

In the context of the rapid development of the integrated circuit industry and artificial intelligence technology,the MCU control chip plays an important role in the collection,calculation,and transmission of information and data.The diversification and complexity of its application scenarios have led to the design of the MCU control chip.The scale and clock frequency continue to increase,which puts more stringent requirements on the quality and power consumption of the clock network structure.Based on the HHGRACE 0.13μm process,this paper designs a 32-bit MCU control chip for the aerospace industry control field.The chip has a maximum frequency of 83 MHz,a design scale of 600,000 gates,an area of 4856μm*4931μm,419input/output ports,14 IP modules,including two 512 KB flash memories(Flash),a phase-locked loop(PLL),a 12-bit digital/analog converter(ADC),four 256 KB and three 128 KB static random access memories(SRAM),three 1MB true random number generators(TRNG).Aiming at the two stages of Placement and Clock Tree Synthesis in the digital back-end design of the MCU control chip,this paper proposes a design plan for optimizing the clock tree network structure,which mainly includes the following four points:(1)In order to reduce the power consumption of the clock tree network,this paper proposes a method for the placement constraint configuration and fixed placement of the clock divider cell before Placement.The results show that the power consumption of the clock network is reduced to 94.66 mw,which is reduced by 21%compared with the traditional CTS,and does not affect the timing path.(2)In the clock tree synthesis stage,due to the use of testability to design Scan Test,there is a scan chain inside the chip,which leads to crosstalk between the clock tree network structure in the function mode and the scan mode.In this regard,this article proposes a method to configure a stop pin on the scan clock input of the multiplexer.The results show that compared with the traditional clock tree network structure design,the worst negative slack(WNS)of the setup time is reduced by 76.8%,and the total negative slack(TNS)is reduced by 68.9%.The total number of time series violation paths is reduced by45.9%;the worst negative slack(WNS)of the hold time is reduced by 43.8%,the total negative slack(TNS)is reduced by 38.5%,and the total number of time series violation paths is reduced by 38%.(3)Through the analysis of the timing results of the synthesis phase of the clock tree,in order to further improve the timing optimization,this paper proposes to set the clock pin(CLK pin)of the frequency division cells in the clock frequency division module to ignore the pin(Ignore Pin)to intervene in the clock network structure.The timing results based on this method show that the WNS of the setup time is reduced by 4.4%;the WNS of the hold time is reduced by 20.9%.(4)Based on the selection of the traditional clock tree synthesis stage construction cell,under the premise of meeting the timing closure,reduce the power consumption of the clock tree,and propose a design method of mixing buffer and inverter to construct a clock network structure.The results show that the power consumption of the clock tree network is reduced to 94.66 mw,and the total power consumption within the chip is reduced to 395.7mw,which is 19.2% and 9.9% respectively reduced compared to the traditional clock tree synthesis.