Effect Of Interface Traps On The Mobility And Threshold Stability Of SiC MOS

SiC MOSFETs play an important role in high-power,high-temperature and high-frequency applications due to their unique materials and excellent structure and performance,but due to their high concentration of traps,the mobility and threshold voltage are greatly constrained.And because of its high working environment temperature,studying its high temperature characteristics also has more important practical significance.At present,research in this area at home and abroad is not perfect enough,which limits the large-scale application and commercialization of SiC MOS devices.Therefore,in order to improve the performance of SiC devices and improve their reliability,SiC MOS devices need to be modeled,and theoretically analyze and improve it.This article mainly from the following aspects of modeling and research:SiC MOSFETs play an important role in high-power,high-temperature and high frequency applications due to their unique materials and excellent structure and performance,but due to their high concentration of traps,the device has poor gate stability and low mobility.Due to the high ambient temperature of the SiC device,it is of great practical significance to study its high temperature characteristics.At present,research in this area at home and abroad is not perfect enough,which limits the large-scale application and commercialization of SiC MOS devices.Therefore,in order to improve the performance of SiC devices and improve their reliability,SiC MOS structure devices model need to be built and theoretically analyzed and improved.Based on the carrier tunneling model,the FP thermionic emission model and the SRH?Shockley-Read-Hall?composite model,the traps containing SiC/SiO₂ interface traps(N_it)and the oxide-based near-interface traps(N_iots)inside SiO₂ were established using the Sentaurus software.The C-V and I-V simulations perform using the model to investigate the effects of N_iot and N_it on gate stability and channel mobility.The simulation results show that N_iot is the main cause of the threshold voltage(V_TH)shift,and its impact on the mobility reflect in the capture of carriers;N_it is due to the faster release of carriers,offset of V_TH effect is smaller,and the effect on the channel mobility reflect in charge trapping and Coulomb scattering.The simulation studies the effect of N_iot's physical position and energy level position on the CV hysteresis voltage,and the temperature vs.interface trap charge(Q_its)and near-interface trap charge(Q_nits)on MOS structure C-V and I-V from the perspective of experimental and simulation integration.According to the established MOS structure model,the influence of traps with different physical positions on the C-V hysteresis curve is explained from the perspective of the charge tunneling probability,the trap emission time constant?_e and the trapping time constant?_c.When the trap is more than 6nm from the interface,the trap can no longer trap the charge.When the trap's physical position is less than 6nm,the concentration of Q_nitsits increases as the distance between the trap and the interface increases.Considering that the effect of oxide charge on flat band voltage varies with position,the overall hysteresis of C-V reaches its maximum at 3nm from the interface.On the other hand,with the deepening of the trap level in the SiO₂ forbidden band,the overall trapping of Q_nits appears to increase first and then decrease.When the oxide trap level is 1.5eV from the bottom of the SiO2conduction band,trap charge-trapping peaks.After 1.5eV,the effect on the flat band voltage slowly decreases.As the trap energy level is lower than the SiC Fermi energy level,its effect gradually disappears.The simulation and experimental results of I-V show that with the increase of temperature,the threshold voltage and the mobility both reached the minimum and maximum at the same temperature?600K?.The trap charge curve directly extracted from the simulation shows that although the temperature increase according to the formula will lead to an increase in the tunneling probability and a decrease in?_c and?_e,the changes in the three are inconsistent with N_it and N_iot.The reduction of?_e causes Q_its to be released faster.This partially released charge will increase to the inside of the oxide layer because of the tunneling probability,and traps trapped by the oxide layer,making Q_nits and Q_its increase with increasing temperature respectively.In addition,eventually leading to an extreme value of V_TH and field effect mobility with temperature changes.And from the charge trapping conditions obtained by the C-V test,the increase in temperature also exacerbates the asymmetry of the emission and trapping charge curves,resulting in more trapped charge remaining in the oxide layer,which increases the hysteresis of the C-V curve.In order to improve the current SiC test scheme,the influence of different applied bias conditions on the SiC device is studied.When the voltage rise time and the high voltage duration are long,traps will increase the number of trap carriers,which will lead to the threshold voltage.The forward offset increases.When the voltage drop time increases,more trap charge will be released during the falling process,so that the measured device threshold voltage offset decreases.