Test Pattern Generation And Design For Test During FPGA Logic Synthesis

Nowadays, because of the easy reprogramming capability and high flexibility,Field Programmable Gate Arrays (FPGAs) have been widely used in digital systems indifferent areas. However, from the view of testing, FPGAs can not be considered asclassical Application Specific Integrated Circuits (ASICs) due to the typical structureand design flow. In SRAM-based FPGAs, combinational logic is implemented byLook-Up Tables (LUTs), i.e. configurable SRAMs of small size. The failure mechanismand fault behavior in LUTs are very different from those in gate circuits.Built-in-Self-Test (BIST) has been employed for application-independent testingof FPGAs. In most reported methods, only the fault detection in the part of Circuitunder Test (CUT) is considered and several rounds of reconfigurations are needed tocover the whole chip. Motivated by this, a modified method of chain-based BISTarchitecture for LUT is proposed to increase the fault coverage of all involved resources.Compared to existing methods, the efficiency can be significantly improved.Application-dependent testing of FPGA is important to ensure the reliability duringsystem operation. However, classical Automatic Test Pattern Generation (ATPG)methods are not really suitable for FPGAs. This paper focuses on combinational circuitwhich mainly reflects the difference between FPGA applications and ASICs. Anefficient ATPG algorithm for combinational FPGA applications is proposed as anextension of classical FAN algorithm. Test set compression methods are employed tocut off redundancy in the generated test patterns.Additionally, a Design for Test (DFT) method for FPGA applications is proposed,which makes use of the inherent free resources produced in the logic systhesis process.By adding redundant interconnect wires in FPGA applications, the proposed methodcan mask faults in LUT bits and reduce the total number of test patterns needed to testan application with no extra area overhead. This DFT procedure is integrated into thetypical FPGA design flow of Altera Quartus II.