Research And Design Of Low Power SAR ADC For Physiological Monitoring

With the rapid development of wireless sensor network technology,medical care system has obtained new developing opportunities.Wearable and implantable devices are gradually becoming hot research spots in the physiological monitoring field.Users can conveniently carry out health monitoring anytime and anywhere by getting rid of the traditional constraints of fixed time and place.Successive-Approximation-Register Analog-to-Digital Converter?SAR ADC?exhibits a good application prospect for physiological signal acquisition in biomedical fields because it contains fewer analog components and has simple circuit structure.However,the sampling frequency of current SAR ADC is generally high,which is not suitable for low frequency bioelectrical signals.Moreover,the power consumption caused by switch operation during the comparison process is usually quite high,which will restrict the applicable scenarios and the life of the whole chip.To solve the above-mentioned problems,a fully differential CMOS switched-capacitor SAR ADC of 12 bits and 100 kS/s for physiological signal acquisition is studied and designed in this thesis.The key modules of the whole circuit consist of the sampling and holding circuit,differential capacitor array,comparator and successive approximation control circuit.The main content of this thesis can be summarized as follows.1.The requirements for monitoring physiological signals with low sampling frequency and low power consumption are analyzed firstly.Then the SAR ADC is determined as the ADC type for physiological signal sampling.Moreover,a method for reducing the power consumption of SAR ADC is proposed by analyzing the performance and requirements of the physiological monitoring.2.Aiming at the high power consumption problem during the first three comparisons of switching operations in the digital-to-analog converter?DAC?capacitor array,a high-bit split and low-bit compensated differential DAC capacitor array is proposed,which can effectively reduce the switching power consumption during the comparison process by making use of the same capacitance value of the high-bit split capacitor and the sub-high-bit capacitor.Moreover,by controlling the closure of the switches,the value of the redundant LSB capacitor is changed during the last comparison,and thus introducing a new voltage reference source is not required during the last comparison.3.Based on the monotonic switching scheme,a novel switching scheme based on the upper plate sampling is proposed for the high-bit compensated and low-bit split capacitor array,which can solve the high switching power consumption problem during the first three comparisons.Furthermore,by combining with the proposed high-bit split and low-bit compensated differential DAC capacitor array,the successive approximation of the voltage between the two ends of the comparator can be implemented without introducing a new reference voltage in the last comparison process.Therefore,the power consumption caused by switch operations in the sampling process is significantly reduced,and both the number of capacitors and the chip area can be effectively reduced.Simulation results show that the average switching power consumption is reduced by 95.93%,and the area of the capacitors is reduced by 50%compared to the monotonic switching scheme.4.To solve the problem of the increasing common mode voltage during the unilateral sampling of the upper plate,a common mode voltage correction circuit is proposed.The common mode voltage of the SAR ADC can be maintained near V_ref/2 during the comparison process,and thus the linearity distortion of SAR ADC caused by the common mode voltage drift is solved.Furthermore,the gate voltage bootstrap switch is adopted in the sampling circuit,which avoids the switch on-resistance change caused by the changing input voltage,and eliminates the nonlinear change during the sampling process.5.Based on the above-proposed methods,a 12-bit 100 kS/s fully differential CMOS switched-capacitor SAR ADC is finally designed in a SMIC 65 nm CMOS process.Simulation results show that the proposed switching scheme has an energy efficiency about 78.3%higher than the monotonic switching scheme.At a sampling speed of 100 kS/s,the signal-noise and distortion ratio?SNDR?is 62.55 dB,the effective number of bits?ENOB?is 10.1,and the power consumption is 20.18?W.Therefore,the proposed switching scheme achieves better area optimization and power consumption reduction,and can meet the application requirements of physiological monitoring.