Research On 10-bit Nanowatt Successive Approximation CMOS Analog-to-Digital Converter

With the rapid development of large-scale integrated circuits,wearable devices and implantable medical devices are becoming more and more common in our life.These devices have to work continuously for several years or over ten years,so the energy efficiency is required to be as high as possible.Therefore,there has been an increasing requirement for their analog front-end circuits.Analog-to-digital converter(ADC)used to connect analog and digital circuits in these devices,low power consumption has also become its main design index.The successive approximation ADC structure has the highest energy efficiency,so it is the best choice for these devices.The purpose of this thesis is to study capacitor switching schemes and related circuits of low-voltage and low-power SAR ADC.Firstly,the basic theory of SAR ADC is introduced in this thesis,including the current research hotspots of SAR ADC and characteristic index of ADC.Secondly,essential module design methods of SAR ADC are presented.Finally,based on the 40nm 1P8M SMIC CMOS process,the circuit innovation and layout design of the 10-bit low-voltage and low-power SAR ADC are completed.The main innovations of this paper are listed below.Firstly,four capacitor switching schemes are proposed,including two-step two-input comparator structure(TSTC),half-sampling structure(HS),two-step four-input comparator structure(TSFC),and improved two-step four-input comparator structure(ITSFC),which achieve99.83%,98.4%,99.84%,99.56%saving in average switching energy and 76.37%,50%,84.38%,and 81.25%reduction in total capacitance compared to the conventional switching method when applied to a 10-bit SAR ADC,respectively.Comprehensively considering energy efficiency,area optimization,common mode point change,linearity,control complexity,reset energy consumption and parasitic effects,etc.,we finally choose ITSFC switching scheme to complete the overall SAR ADC design.Secondly,double-boosted switches apply to sampling circuit and connected switch to reduce non-ideal effect of switch.In addition,the substrate bias cancellation technology and coupling cancellation technology are added to the sampling circuit,so that the on-resistance of the sampling switch is constant and independent of input voltage.When the supply voltage is 0.4V,the sampling switch achieves 99.29 d B SFDR,80.71 d B SNDR and 13.12 bits ENOB with nyquist input at 10KHz.Thirdly,ultra-low power dynamic comparator uses a cascode current source to suppress the channel length modulation effect,reduce the dynamic offset voltage,limit the change of the comparator delay with the common mode voltage,and save power consumption.Moreover,body-driven technology and cross-coupled inverter improve total transconductance,provide stronger positive feedback,so greatly reduce comparator delay.The maximum delay time is less than 3us,the dynamic delay change is only 0.25us,and the dynamic offset voltage is only 0.28m V with common-mode voltage from 0.5VDD to VDD at supply 0.4V.Fourthly,in order to reduce the power consumption caused by the reference voltage V_cm,a low voltage and low power reference circuit is designed.The simulation results show that when the power supply voltage is 0.4V,SAR ADC achieves67.7 d B SFDR,58.35 d B SNDR and ENOB of 9.40 bits with Nyquist input at 10 KHz.The overall power consumption is 27.6n W,and the maximum DNL and INL are-0.67/0.88LSB and-0.83/0.80LSB,respectively.