Research On Key Techniques Of Highly Energy-Efficient Noise-Shaping SAR ADCs

Over the past two decades,the performance of analog-to-digital converters(ADCs)has improved steadily,which has provided the advantageous fundament of the development of informantion communication technology(ICT).With the booming of the lowpower and smart products,e.g.,Internet-of-Things(IoTs),wireless communcation and sensors,the conventional ADC is hard to satisfy the requirement for lower power,higher speed,high resolution and smaller area,simultaneously.With the continuous advancement in integrated circuit(IC)manufacturing technology,the performance of digital IC has been improved tremendously.However,it brings unprecedent challenges to analog circuits.As the transistor intrinsic gain and supply voltage decreased,it has become the predicament for high-performance analog circuits design.Especially,the conventional high-resolution ADCs,?Σ ADC and Pipeline ADC,depend on the high-gain amplifiers to realize high resolution.From both academic and industrial perspectives,it is of great importance for launching the study on novel hybrid ADCs,which are scaling friendly and highly digital,to overcome the technical bottleneck for analog circuits and promote the development of energy-efficient ADC.Due to mostly passive and digital implemntation,the successive approximation register(SAR)ADCs greatly benefit from the IC technology scaling,which are power-efficient candidate architecture for medium-speed and medium-resolution applications.For highresolution design,their power efficiency degrades due to excessice comparator noise and exponentially growing capacitor digital-to-analog converter(DAC)array.The emerging noise-shaping(NS)SAR ADC hybridizes the conventional SAR ADC with the ?Σmechanism,fusing both merits in power and resolution.It provides a preferred choice for corealization of high resolution and power efficient with the IC technology scaling.The dissertation makes a detailed analysis on non-idealities of SAR ADC,furtherly disscuses the opertional principle and methods for noise-shping technique,proposes a cascaded integrator feed-forward(CIFF)NS-SAR ADC and two NS-SAR ADCs based on error-feednack(EF)structure and realizes the energy-efficient target with in-band noises suppressed and resolution improved.The main contributions of the dissertation are as follows:(1)At the beginning of the dissertation,the non-idealities of SAR ADC is analysed,including sampling thermal noise,DAC capacitive array mismatch,comparator noise and so on.The NS principle and method are discussed subsequently,including CIFF NSSAR ADC and EF NS-SAR ADC.A compact and PVT robust opamp-free NS SAR ADC based on CIFF structure is proposed.The proposed NS SAR ADC adopts extra one passive feed-forward path summing with the minimum modification to a standard SAR ADC to realized second-order noise shaping.Compared with the previous works,the k T/C noise sources of residue sampling and first-order integration are obviated,and the ADC input referred noise is reduced by 51.9%,resulting in higher SNR and resolution with the same SAR ADC structure.In the integration path,it implements 4× passive gain by capacitive charge-pump technique that compensates the partial loss of residue voltage and relaxes the specifications of comparator,resulting in a 75% reduction in comparator consumption.The proposed NS architecture is based on passive switched capacitor.Through the behavioral modeling and simulation results,it exhibits the superior precess,voltage and temperture(PVT)robustness and NS effect with the zero of its NTF located at z = 0.8.A SQNR of 104 dB is achieved at the OSR of 14.(2)We propose a EF NS-SAR ADC based on finite impulse response(FIR)filter.Different from the CIFF NS-SAR ADC reslized by high-performance infinite impulse response(IIR)filter,the proposed design employs a set of delay capacitors and a unity-gain buffer(UGB)to realize the aggressive NS architecture,which reduces the circuit complexity.The UGB avoids the attenuation during the residue sampling,and passive capacitor summation eliminates the usage of multi-path comparator,the aformentioned techniques improve the efficiency of noise shaping and address the device mismatch issue,therefore,the resolution of ADC is obviously promoted.Verified by simulation in 65 nm 1P9M CMOS process,a standard first-order EF NS-SAR ADC is realized.The simulation results show that the proposed design achieves a peak SNDR of 81 dB,a power consumption of 183.66 μW,yielding schreier figure of merit(FoM)of 176.32 dB,with the supply voltage of 1.2 V and oversampling rate(OSR)of 16.(3)We propose a standard second-order EF NS-SAR ADC,which demonstrates compact and flexible structure.Taking place of the conventional UGB based on amplifier,a new differential UGB originating from source follower is proposed,which simplifies cirsuit design,enhances scaling compatibility and maintains the advantage of SAR ADC in power efficiency.The proposed NS-SAR ADC is simple to design,and delay capacitors are operated in ping-pong manner to perform EF path,which can be extended to high order.Fabricated in a 65 nm 1P9M CMOS technology,the prototype NS-SAR ADC achieves a peak SNDR of 79.3 dB,yielding schreier figure of merit(FoM)of 176.32 dB and Walden Fom of 11.99 f J/step,when operating at 1.2 V with 625 k Hz input bandwidth,and it is suitable for Io T and wireless communcation applications.