Design Of High Performance Clock Tree Based On ARC Control System Architecture

In the past decades,the development of integrated circuit was especially rapidly,break through results have been achieved both in terms of process technology and architecture.However,the progress of technology has also increased the difficulty of integrated circuit design,more and more challenges were brought in current clock generation and distribution design.First of all,the requirement of system performance getting higher and higher result in a higher system clock frequency,higher clock frequency will bring more dynamic power consumption.Secondly,the development of process technology has made the line width smaller,but also brought more on-chip deviation effects.If it cannot be handled correctly,it will cause a tremendous harm of the clock performance.Finally,the advanced semiconductor process allows more devices to be integrated with the added burden of clocking.At the same time,the chip area increases and the device's high level of integration will lead to longer and longer clock routing,clock tree will more and more difficult to be well balanced.Therefore,the stability of the clock design affects the stability and reliability of the integrated circuit to a large extent.How to manage the clocks of each module in the system uniformly has become an significant and urgent problem to be solved.Based on the ARC processor control subsystem in the baseband chip of mobile phone,this paper designs a special unit to manage the clock according to the system requirements of the application platform.This clock management unit has the main goal of delivering high-performance clocks to other modules in the subsystem.And combined with the actual working status of the chip,the corresponding frequency adjustment is performed to achieve the purpose of reducing the dynamic power consumption of the chip.First of all,this paper introduced the traditional clock generation and clock low power control methods,and applied in the clock generation unit design based on ARC control system architecture.Simultaneously,the paper analyzed the low power control methods used in the clock generation design currently.Including glitch free switching technology between two clock sources,clock gating technology and frequency divider circuit design.Secondly,this paper studies the low power consumption strategy of clock management and the corresponding logic design based on the system architecture.The clock requirements of each module are analyzed,and the synchronous or asynchronous relationship between all clocks is defined.And inserted multi-level clock gating,PLL automatic control circuit,hardware auto-request clock source,glitch-free clock switching,DVFS(Dynamic Voltage and Frequency Scaling)Clock generation and low-power clock control technology to design clock generation and distribution unit.Rational insertion of DFT(Design for Test)logic allows the clock to be controlled during testing.Finally,the clock generation and distribution unit was verified.The Spyglass tool was used to perform cross-clock domain checking.The DVE simulation tool verified the correctness of the function and the STA(Static Timing Analysis)tool Prime Time verified that the clock design meets the expected timing requirements.Through the practice of the project,the clock design method proposed in this paper can facilitate the project to quickly determine the clock management program,and achieved great results in the clock generation and low power control design.In summary,this paper has certain reference value for the design of clock generation and distribution unit of chip design.