| As an important part of the design of radiation hardened integrated circuits(ICs),the soft error rate(SER)evaluation has always been a great issue of scholars at home and abroad.With the technology scaling,Single event multiple transient(SEMT)has become a common issue,which not only severely affects the accuray of soft error rate evaluations,but also makes the research for SEMT hardened technique become an urgent need.In this paper,single event multiple transient is focused on.Research works on soft error rate evaluation and integrated circuit hardened technique have been done.The research works of this paper consists of the following aspects:(1)This paper presents a soft error rate evaluation approach considering single event multiple transient,which is based on TCAD+Verilog simulation approach.In this approach,TCAD simulation tool is used first to collect the SET pulse library,then parameterize the evaluation circuit cells and generate SET pulse model by using algorithm.At last,copy the evaluation circuit and load the SET pulse model into the test model for Verilog-based circuit simulation.The soft error rate can be obtained from the comparison with the output of the golden model.Compared with traditional soft error rate evaluation approach,this approach can simulate soft errors caused by single event multiple transient more accurately,and it is fast enough to be applied to the soft error rate evaluation of large-scale integrated circuits.(4)This paper presents an integrated circuit hardened approach considering single event multiple transient,which is based on the soft error rate evaluation approach proposed in this article.At first,lock the sensitive nodes of circuit by using algorithms,then re-layout the cells of sensitive nodes and increase the distance between sensitive cells,to mitigate the generation of single event multiple transient.This approach has little effect on area,power consumption and timing of circuits,which can be applied to harden large scale integrated circuits,which can mitigate or even eliminate the soft errors induced by single event multiple transient after iteration.The soft error rate evaluation approach presented by this paper can apply to large scale integrated circuits in different process,which have good versatility,solving some problems of integrated circuit soft error rate evaluation in advanced process and providing a reliable solution for large-scale integrated circuit soft error rate evaluation.The integrated circuit hardened approach presented by this paper can effectively reduce soft errors caused by single event multiple transient while keeping the area,power consumption and timing of circuits almost unchanged,which can be used in large scale integrated circuits design engineering. |
