Single Event Multiple Transient Effect And Its Mitigation In Nanometer CMOS Integrated Circuits

With the continuous growth of the aerospace industry in our country,rad-hardened integrated circuits(ICs)research develops gradually.Radiation effects and integrated circuit rad-hardened design have become hotspot and difficulty in academia and in industry.In recent years,the demand of aerospace applications for data and image processing grows sharply,which makes advanced nanometer process to be inevitable in future aerospace applications.However,in nanometer scales,device density increases,work frequency of ICs increases,and the supply voltage is decreased.Therefore,single event transient(SET)generation and propagation become more and more complex,and single event multiple transient(SEMT)become a common modality of SET,and then the total soft error(SER)is increased.In this article,SEMT is focused on.Based on a theme of "SEMT mechanisms?SEMT experimental characterization?SEMT mitigation",SEMT in nanometer ICs is studied,and four aspects are shown as follows:(1)SEMT interaction in the same path is researched in this paper,and there will be over two SETs generated in the same path,these SETs will overlap with each other and then PQ(pulse quenching)effect and PBAN(pulse broadening after narrowing)effect are possible.By Geant4 simulation in different technologies,the results indicate that the probability of PBAN increases with technology scaling down,and in 22 nm technology,the transient near the input in a SEMT has the probability of >60 % to be quenched,and these quenched transients still have the probability of >30 % to be broadened again.(2)The SEMT generation in non-storage nodes in sequential logic is also researched in this paper,and the single event double transient(SEDT)generated in data input and clock input of a flip-flop is founded.The heavy ion experiments in 65 nm twin-well bulk CMOS process does not only verify this mechanism,but also indicate that its contribution to the total SEU might be over 10 % in 65 nm twin-well bulk CMOS process.Meanwhile,the simulation of different technologies show that the threshold energy for the occurring of this mechanism decreases as technology scales down.(3)The universal SEMT measurement is researched in this paper as well.The SEMT generation in combinational logic can be realized with the array of vertical chains based on arbitrary cells in a standard cell library,and the SEMT on-chip capture can be realized by the combination of several SET on-chip capture circuit.Based on inverter,the Uni VIC(uniform vertical inverter chains)test structure in 65 nm twin-well and triple well bulk CMOS process is constructed.Heavy ion experiment results showed that: a)with LET less than 40 Me V·cm2/mg,there are at most three transistors impacted in 65 nm process,that is,there is at most single event triple transient(SETT)generated;b)the occurring probability of SEMT in twin-well structure is no more than 30 %,and the charge sharing intensity reaches to 80 %~90 %;c)the occurring probability of SEMT in triple-well structure is no more than 55%,and the charge sharing intensity reaches to 75 % ~ 80 %.(4)The SEMT mitigation technique is also researched in this paper,and the mirror image(MI)technique and the seamless guard band(SGB)technique is proposed,and then the cell-level hardening strategy is summarized.The strategy points out that the SER of any circuit can be reduced by applying SET/SEMT hardening technique to the standard cell library,and various hardening technique can be employed based on the circuit feature of the cell.The MI technique is mainly suitable for those cells with two stages(such as NAND gates),it enhancing charge sharing between two stages is beneficial for utilizing PQ effect to help the generated SEDT cancel each other.The simulation results indicate that the width of SET pulse generated in anterior stage can be mitigated over 25 % while the width of SET pulse generated in posterior stage can be mitigated about 10%.The SGB technique is mainly suitable for simple cells in a standard cell library.The simulation results show that SGB technique can mitigate SEMT generation completely with the LET less than 40 Me V·cm2/mg in 65 nm technology,and the SET pulse width can be mitigated about 50 %.Though there is several hundreds of research about charge sharing before,the research about SEMT generation and propagation in combination logic and the effect of SEMT on SER is limited except for MCU(multiple cells upset).By one hand,the SEMT measurement is improved in this paper,and a universal SEMT measurement approach is proposed,which is suitable for both SEMT from any standard cell and SEMT in the next generation CMOS technology.By another hand,the SEMT generation and SEMT propagation is discovered partly in this paper,and the SEMT mitigation technique is proposed,which has given out much data for SER evaluation and SER prediction.Thus,the precise of SER evaluation can be improved,and the hardening design of nanometer ICs can be improved as well.