Design And Implementation Of High-rate Data Acquisition System

THe high rate data acquisition is a important part of modern information technology,collect and process the information people need.With the rapid development of electronic science and technology.High rate data acquisition system gradually to the high sampling rate high bit wide and high rate PC interface development trend.The purpose of this paper is to design a high rate data acquisition with high-rate ADC,high-rate DAC and communication with host computer through Ethernet interface.This system is divided into 4 parts,including:system clock module,high-rate ADC module,high-rate DAC module and Ethernet module.The data processing of the high-rate ADC module and the high-rate DAC module and the MAC function of the Ethernet module are all realized by FPGA.The FPGA is divided into three parts in the system.The system clock module provides the working clock for the high-rate ADC module,the high-rate DAC module and the Ethernet module.PLL chip frequency doubling external crystal oscillator to produce the working clock.AVR through the SPI interface configuration PLL operation mode.The high-rate module function is the high-rate ADC chip to collect signals and transmit to FPGA.The FPGA process sampling signals.The processing of FPAG is data reception,unified clock domain and channel synchronization.The Ethernet module sends the data collected by the high-rate ADC module to the PC.The MAC function is implemented by FPGA.The physical layer function is realized by PHY chip.The network protocol uses the UDP/IP.The high-rate DAC module will be stored in the FPGA signal data in the digital analog conversion to generate analog signals.FPGA completes data storage,data reading,data interleaving and data transmission in this module.This high-rate data acquisition system finally realizes the high-rate ADC work in three mode,single channel 5Gsps,dual channels 2.5Gsps or four channels 1.25 Gsps sampling,8bit sampling bit.The high-rate DAC completes2.5Gsps sampling and sampling-width 14 bit.To achieve interactive data with the PC through Ethernet.In the end of this paper,the improvement of the system if put forward according to the deficiency of the design and test results.