Design And Implementation Of Ethernet High-frame Measurable Camera

In order to solve the complex problems of traditional animation production technology, a high-frame measurable camera based the Ethernet is designed, which is related to the image process and multiple moving targets tracking technologies. This system uses the image measurement technology to get the moving targets'barycenters from the multiple directions tracking in the real time, and then the barycenters coordinates will transmit to the computer. The reality motions will be translated into the animation motions by using 3D mixture technology. The animation technology becomes easier because of this design.The system uses the FPGA as the core controller, the Ethernet as the transmitted link, the CMOS image sensor as the image acquisition unit. FPGA is XC3S250EPQ208 of Xilinx Corporation, and Ethernet controller is W5300, and the image sensor is MT9P031 of Micron Corporation. The image solution is 720V*1280H and the frame rate is 60fps. The maximum data processing rate can be up to 442Mbps, and the maximum data transmitted rate can be up to 85Mbps. Two pieces of SRAM are used as cache unit to improve the efficiency of the system. Alternate working mode is used for these two pieces of SRAM.The human-machine interface is designed on the VC++ 6.0 platform. It can connect to any terminal in the local area network by UDP transport protocol. The camera is the server while the PC is the client, and the PC can set the camera's working mode, the binarization threshold and the other parameters. Cameras transmit the 8bit gray image to PC in the image mode, and transmit the barycenters coordinates in the image in the measurement mode.The maximum targets in the image are 300 in this design.In order to solve the difficult problem of tracking the moving targets in the real time, First filter the image data and then get the edges information. The result is memorized into the SRAM and calculated the real-time barycenters. All the image process and calculation are done on the FPGA because of its parallel calculation character. The pipeline thought is designed for FPGA to improve the system's operating frequency and calculation efficiency. The barycenters of tested marks can be calculated in the 16ms.