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Design Of High Speed Image Acquisition And Gigabit Ethernet Trasmission System Based On FPGA

Posted on:2018-01-02Degree:MasterType:Thesis
Country:ChinaCandidate:H WangFull Text:PDF
GTID:2348330515455118Subject:Control engineering
Abstract/Summary:PDF Full Text Request
High speed image acquisition and transmission system is designed based on the powerful parallel data processing capability of FPGA and the high speed and long distance transmission of Gigabit Ethernet,It can collect and transmit the remote image data in real time.Image acquisition and transmission system is of great significance to the development of the technology of moving target detection,navigation and guidance.The main research work of this paper includes:1.High-speed image acquisition and transmission system consists of image acquisition circuit board and CMOS image sensor OV5640 two parts.The image acquisition circuit board consists of the main controller EP4CE15F23C8N,DDR2 memory MT47H64M16,Ethernet interface control chip RTL8211 EG and expansion port and other components.2.The system of the image acquisition circuit board made a physical production.Firstly,the FPGA core circuit,DDR2 memory circuit,Ethernet interface circuit and the expansion circuit are designed.Then according to the characteristics of each part of the peripheral circuit connection of the overall PCB design,It mainly includes the design of the laminated structure,the layout and wiring,the impedance calculation and the power plane division.Finally completed the circuit board welding.3.The software of the system is designed and written.The design is completed on the Quartus? 12.1 software development platform,using the Verilog hardware description language to design the software program of the system,it mainly includes the design of OV5640 image acquisition module,DDR2 image storage module,Ethernet image transmission module and clock management module.The system workflow is:Firstly,CMOS image sensor image data collected for the bit width of 32 bits of data,then the data storage method by using ping-pong operation to DDR2 SDRAM,DDR2 to achieve the image data cache,the cache in the DDR2 data transmission to a machine on the PC through UDP protocol.Through the test of each module and the combination of the system,the test results show that the system can realize the real-time and high-speed data acquisition and transmission.
Keywords/Search Tags:FPGA, gigabit Ethernet, real time, DDR2, high speed image acquisition
PDF Full Text Request
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