Rate Adapter Design And Implementation Of Tdm Channel Carrying Ethernet Business

In the current telecommunication system and railway communication system, there exist numerous standard interfaces of TDM system, such as El. The method of using existing El channel resources to transmit the Ethernet information endows strong application value and practical significanceTo transmit high-speed Ethernet data through low-speed channel, the critical task is to solve the rate adaption. This paper proposes a design scheme of rate adaptor which is based on an Altera Cyclone series FPGA fitted with PHY chips as well as an SRAM of external large capacity The PHY chip manages transceiver of Ethernet data in physical layer. The external SRAM is used as a buffer between the high-speed and low-speed data channel, while the FPGA is used as the control core of the whole system.This paper not only presents main part of schematic diagram of the adapter, but also highlights the functional module design of FPGA. By configuring the physical layer chip reasonably, the standard code from twisted pair can be transmitted to the MAC layer through the standard MⅡ interface, and the data from MⅡ interface can also be sent back to the twisted pair after encoding. The difficulty in the design is how to ensure data transmit error-free between25Mbps MⅡ interface and2.048Mbps E1interface. In the high-speed data transmission via a low-rate channel, there inherently exist the problem of data cache, which can be solved by using an external large capacity SRAM controlled by FPGA present in the design scheme. Beyond that, FPG can send and receive data through the interaction between MⅡ interface and PHY. After4/8transformation, HDLC framing and parallel serial conversion, the Ethernet data received from MⅡ interface can be transmitted to the receiving terminal through serial data at the rate of2.048Mbps, while those2M serial data can be transmitted to PHY after synchronous clock extraction, serial parallel conversion, HDLC reframing and8/4transformation.The paper presents the result of debugging and validation after finishing designs of hardware and software. By combining two adapters to set up a data channel at rate of2.048Mbps between them, data were successfully transmitted between two PC which are linking to the adapter.100Mbps Ethernet data were successfully transmitted via a2.048Mbps channel between two rate adapters.