14bit 250MS/s ADC Front-End Design And Optimization

Pipeline ADC plays a significant role in broadband and high precision analog-to-digital convertor,therefore,it is the first choice for a high-speed and high-resolution design.For the application in multi-channel system,it is important to realize a lower consumption of Pipeline ADC with high performance.A conventional Pipeline ADC usually has a Sample-and-Hold Amplifier(SHA)with N-stage structure behind.S&H is a unity-gain amplifier with the function of sampling and holding the input signal,then the input signal was transferred to the first stage.However,SHA introduces noise and extra power consumption.which is detrimental to the high performance and low consumption Pipeline ADC design.To meet the requirements of low power consumption design,the SHA is abandoned,but this design leads to a problem of aperture error.To solve the problem of aperture error,the technique of eliminating aperture error is introduced.But the technique of eliminating aperture error increases the complexity of the circuit design,especially in the timing design,threshold voltage,and so on.Thus,it is important to the optimization design of the front-end circuit,which includes:using the capacitor-split technique to generate the threshold voltages,which can contribute to the low-power consumption;A novel timing design—three-phase clock is proposed,which can benefit to the transition of front-end circuit;The front-end circuit introduces an interpolation structure for comparators,which can decrease the amount of preamplifier.Besides,the calibration circuit for capacitance is introduced in the circuit optimization,and the simulation result shows that,SNDR is improved by 30dB,and SFDR is improved by 26dB after introducing the calibration circuit for the sampling capacitance.The input buffer is introduced in the front-end circuit design,to make the ADC be better driven in the design of broadband and improve the performance in the cases of the high-frequency input signal.In order to implement the design of high performance ADC,the comparator calibration technique is introduced in the front-end circuit design to calibrate the mismatch between the preamplifiers.In layout design,the overall layout,the protection to the sensitivity signal is given in both distribution and isolation aspects in the optimization of the layout.The area of first circuit stage is 0.528mm×0.515mm.The supply voltage of the chip is 1.8V.From the Simulation of the parasitic capacitance of the layout,the result is achieved as the following:the ENOB is 13.77dB,SFDR is93.08dB,SNDR is 84.66dB,when the input signal is 4MHz.The power consumption is73.2 mW,when the input signal is 113MHz,ENOB is 11.61dB,SFDR is 75.18dB,SNDR is 71.66dB.The simulation result indicates that the goal of low-power high-performance circuit design is achieved by optimizing the front-end circuit and the layout.Another assignment of this paper is to optimize and test the 11bit 200 MS/s Subrange SAR ADC.The optimization mainly contains narrow band reference buffer and the charge-compensation circuit optimization.The area of this chip is 0.03mm~2.When the chip is tested,the output data is sampled by FPGA.The result of the test is:the power consumption contains buffer consumption is 3.91mW,with the supply voltage is 1.2V.When the CCU is enabled,and the sampling rate is 200MS/s,the SNDR is 59.5dB and the SFDR is 67.0 dB,with the input signal is 2.4MHz.when the frequency of input signal is 70MHz,the SNDR reaches 56.2dB and the SFDR is73.7dB.