Design Of ∑-Δ A/d Convertor With Adaptive Calibration

The delta-sigma (∑-Δ) approach for analogue/digital conversion is currently of great interest because of its applicability in VLSI signal processing. The approach gives a good compromise between high accuracy, robust stability and speed.Based on the existent∑-ΔADC technologies, this article is to propose a 12 to 16 bits ADC, used in audio processing chip. A high-pass modulated MASH 1-1-0 structured∑-ΔADC circuit and its strength in performance, design and manufacturing is demonstrated and then compared to other module.The second part, the instinct default in ADC manufacturing is shown which can severely degrade the performance of the ADC circuit. The difference between the real circuit and the design model due to the capacity mismatching, finite gain of amplifier and other analog mismatch can be simulated by MATLAB. It shows that a 2% mismatch can cause up to 60% percent performance loss, from 16 bit resolution down to 7 bit.Focusing on the inevitable errors introduced by circuit manufacturing, this article bypassed the common design though working on optimizing analog part. It innovatively introduced an adaptive algorithm, LMS, in the digital filtering part of MASH structure to calibrate the analog errors.After the emulation in MATLAB, the digital adaptive filters can well calibrate the errors in analog part and then recover the performance at 16 bit.This article proposed a different way to recover the performance by a simple MASH ADC design regardless of the technologies.