Investigation On Key Issues Of Analog Front End In High Speed Links

In the past decade, advances in integrated circuit fabrication technology, coupledwith aggressive circuit design, have led to exponential growth of on-chip processingspeeds. On the other hand, the scaling of chip-to-chip data rate in high speed links,especially analog front end (AFE) of high speed links, is increasingly challenging due toband-limited transmission channels and noise, which has continually caused bottlenecks ofoverall system performance at various levels of system hierarchy. Therefore, thechallenges and demand associated with overcoming reliability, power consumption andcost issues in AFE of high speed links have caused a boom in development of techniquesand systems that can improve the efficiency of data communication.This thesis aims to explore new solutions at both circuit and system levels, to addressthese challenges posed by AFE of today’s high speed links. To begin with, how theperformance of high speed links depends on different components within the links isanalyzed. Channel models and various channel impairments that impact link reliability areevaluated. Then, designs of transmitters and receivers are reviewed, the objective of whichis to derive the critical issues that degrade signal integrity, cost and power consumptionperformance of AFE in high speed links, and provide theory basis and motivation for thethree corresponding researches as follows.Firstly, the trend in state-of-the-art high speed links is towards higher speeds andhigher densities, which reflects as dramatically increased driving strengths of transmitterdrivers and number of I/Os on the chip. The result is a large amount of simultaneousswitching noise (SSN) in the power/ground connections, making SSN one of the majorfactors that shrink signal integrity of high speed links. Moreover, since the variability ofload transmission line characteristics, i.e., the capacitance of the load, renders it verydifficult to optimize driver driving capability, a transmitter driver without loadadaptability will overdrive the load or provide less than required driving strength, whichhas become another major limiting factors of signal integrity in high speed links.Therefore, a new transmitter driver with low switching noise and load adaptability isproposed. Thanks to an innovative combination structure of two driving stages, the proposed driver can reduce switching noise and output ringing with no penalty on signaltransmission speed. Furthermore, the driver can automatically adjust the total drivingcapability in response to variation of loading condition, the load adaptive method is simpleand effective. The proposed transmitter driver has been designed in a90nm CMOSprocess. Simulation results show that the proposed driver reduces ground bounce by6.5%~17.6%and output ringing by3.8%~10.9%relative to the controlled slew rate (CSR)driver, which is one of the commonly practiced techniques for transmitter driver.Meanwhile, it achieves4.1%~53.5%improvements in ground bounce and2.9%~15.2%reductions in output ringing compared with those of the AC/DC driver, which is a driverwith similar complexity and highly accepted by academia.Secondly, cost is another critical issue that the design of AFE in high speed links hasto take into account. The incompatibility of a large variety of standards in high speed links,which have been developed to standardize data transmission, acts as one of the significantcauses to growing cost of high speed link design. This is because manufactures arerequired to stock different transmitter driver elements for each standard corresponding todifferent applications. Thus, there is an increasing need to provide a switchable transmitterdriver that can function properly for versatile interfaces. Aiming at flat panel display (FPD)application as an example, this thesis proposes a switchable transmitter driver toovercome disadvantages of the prior arts. In particular, a novel swtichable transmitterdriver is realized by designing a standard selection control circuit, an output differentialvoltage calibration loop, and a common mode feedback circuit based on a90nm CMOSprocess. Simulation results show that the proposed switchable transmitter driver workswell among mini-LVDS, RSDS, and PPDS standards.Finally, as data rate of high speed links continue to increase relentlessly, the designof AFE in high speed links are facing grand challenges from both power consumption andreliability interlinked with signal integrity. Besides, while conventional designmethodology is struggling with increasing difficulty to address these issues, it usuallyresults in over designed and power-hungry solutions. This has motivated the explorationon a new methodology, which is referred to as system assisted analog mixed-signal(SAMS). The SAMS approach is distinct from what is done today, which treats the AFEin the links as transparent waveform preservers, i.e., meeting a fidelity criterion. In contrast, by focusing on the ultimate goal of achieving reliable information transfer, theAFE blocks in a SAMS design paradigm are designed as part of the overall system goal tomeet a detection criterion. Specifications derived from the system-level detection criterioncan be much more relaxed than those resulted from the waveform fidelity criterion andthus significant power savings can be expected. Applied in analog-to-digital converter(ADC) based high speed links, where low power and high speed ADCs areparticularly difficult to design by using traditional fidelity criterion, the promise ofSAMS design philosophy has inspired the innovation of BER-optimal ADC. Thequantization thresholds of a BER-optimal ADC are set to minimize the bit-error-rate(BER), the ultimate system-level metric of a high-speed link. To verify the performance ofthe BER-optimal ADC, performance comparison has been drawn between a BER-optimalADC based link and conventional ADC based link, both of which are constructed with theproposed AFE model that captures major circuit non-idealities of flash ADC. It is shownthat to achieve the same BER as that of the conventional ADC based link, theBER-optimal ADC based link can offer power savings of75%in the variable gainamplifier, and50%in both of the ADC and the transmitter driver. Furthermore, theBER-optimal ADC can relax specifications of ADC components in terms of reduction insampler bandwidth and saving of latch stages. Finally, a4GS/s4bit Flash ADC chip isimplemented on a90nm CMOS process, the purpose of which is to verify the benefitsof SAMS methodology and the BER-optimal ADC based link by silicon. Post layoutsimulations demonstrate that the ADC is successfully designed with both goodsignal-to-noise-plus-distortion ratio (SNDR) performance and robustness.