A Gate-level Power Estimation Method And Optimization Strategies

Greatly improved with the complexity of the SOC, including the size, frequen cy, level of integration, level of technology (65nm,22nm), the IC industry into th e era of deep sub-micron and nano-technology, the process of progress on the desig n method of learning proposed new challenges. VLSI designers in the past mainly c oncerned with the size and speed, now, due to the rapid growth of modern commu nications and consumer demand for products, especially large numbers of wireless devices and portable products, IC’s high-performance, small size, especially the lo w power consumption of a higher demand。Power and speed、area together has become a central concern of VLSI designers。Power analysis and optimization of t wo main parts of the low-power design issues in VLSI. Power analysis issues conce rn the different stages of the design process can be an accurate estimate of power consumption, to ensure that the design does not violate the requirements of the desi gn power, and if the design power is not up to so early in the design can make t o optimize approach. At present, there are many power estimation methods and E DA tools, the paper studies the different power analysis methods, and different sta ges of power estimation methods, maximum power and average power estimatio n methods, and application of the clock gating in the low power consumption de signThe main content of this paper:At first, introduce in the CMOS digital circuit, the main power consumption c omes from two sources:the first referred to as static power, the second called dyn amic power. Export their own formula, and proposes some effective methods of re ducing power consumption of each other.Then, to explore the power consumption of the chip in the system, this is our most concern.Secondly, is discussed in the circuit design process in different stages of power estimation method, the significance of such estimates. This estimation is often a t rade-off between accuracy and efficiency, according to the specific circumstances o f different stages, the flexibility to use different estimation methods. A good estim ation method or process is very important for the efficiency of the design of a low -power chip.In the third part, introduce the methods and processes of the RTL-level powe r simulation file to estimate the power consumption of gate-level netlist, this metho d is very effective for improving the efficiency of the chip design, then discusses t he problems and challenges encountered in. Here we described in detail from a de sign of low-level module to its top-level module, the power estimation process. Refe rred to in Part IV when the gate-level power cannot meet the design requirements c an be taken to optimize the power consumption of the circuit. Power optimizatio n consists of two main parts, a dynamic power optimization, a static power optimi zation. Use the the Synopsys company’s tools have a lot of optimization methods, su ch as insert clock gating circuit, the use of different threshold voltage devices, cloc k tree synthesis, depending on the situation decided to use a buffer or inverter or w ill use both to build the clock network, and so on. And a detailed description of se veral gate-level power optimization process and the scripts will be used.