The Design And Realization Of Power Controlling Unit For M-DSP

As the semiconductor manufacturing technology develops rapidly, power consumption problem has become one of the serious challenges in modern DSP chips design. The use of low-power technology in chips is the most effective way to solve this problem. In view of meeting performance requirements to realse the chip's power consumption, the rational utilization of these techniques in the chip design has played an important role to improve the DSP overall performance, expand the range of application and application area.M-DSP is a high-performance multi-core 32-bits DSP chip that is designed by the research institute of microelectronics of National University of Defense Technology independently. It integrates 8 high-performance CPU Cores and large-capacity on-chip memory and a lot of other peripherals like DDR, SRIO. The main goal of this thesis is to develop a Power Controlling Unit(PCU) for M-DSP, which can realize the control of power consumption and meet the high-performance low-power application requirements of the whole chip.According to the analysis of M-DSP's architecture and low-power design requirements, this paper made a partition mode of power domain and clock module for the entire chip, put forward a power management scheme based on domain partition and use of various power-controlling technologys, which led to the successful design of PCU's power-controlling logic and state-translating logic. For the power management of power domains, the power of the domain controlled by Power Shut-Off(PSO) that is based on Common Power Format(CPF) of the Cadence. As for the clock management of peripheral modules, it managed the input clock of the module by clock-gating technology and controlled the module's low-power state by reset signal. For the power management of large-capacity on-chip memory, it could make the realization of power-sleep low-power mode of the memory by controlling the pins. In addition, in order to realiza the power consumpution management of processors, it controlled the clock of entire core and the CPU's clock by clock-gating technology. In order to ensure the normal operation of the chip 's other parts when controlling a target module realize low-power mode, PCU used multicore sharing mechanism that solved the access-violation by memory-protection and cleared the request and response signal through req-ack mechanism.Finally, this thesis combined the verification with software simulation and FPGA emulation to do the functional verification and timing verification work for the PCU controller. It also made a quantitative analysis for the power optimization effect of the PCU. As the verification result showed that the PCU controller, which developed in this paper, had a correct function and met the expected goals of controlling the power and clock of the chip. The PC U had a proper power optimization effect and met the requirements of the design.