Design And Verification Of Platform Activity Controller Based On Low Power Consumption

With the continuous optimization and upgrading of smart products,people are increasingly demanding mobile phone baseband chips.Power consumption is an important aspect that determines chip performance.Mobile devices such as smart phones serve as terminals for information and capital transfer,bringing great convenience for work and life.The increasingly high performance requirements of smart products have also made it an important design goal to reduce product power consumption and increase product integration.In this way,the hardware design for the low-power SOC chip comes into being.The platform activity controller is an interrupt processing control unit under the CPU subsystem,which aims to reduce the power consumption of the CPU.This thesis was focused on the design and verification of the platform activity controller and evaluates its degree of power reduction.The platform activity controller can specifically support the software,match the activities of certain hardware modules with specific time intervals,and avoid excessive wake-up of the central processing unit,thereby prolonging the sleep time of critical hardware modules and power supplies.According to the design,verification and power analysis sequence of the platform activity controller,the process of chip module design was analyzed by the thesis.The low-power design methods mainly include the following: clock gating design method,gate-level optimization design method,multi-voltage power supply design method and multi-threshold voltage VT method,etc.,which are evaluated in timing,area,architecture,design,verification,place and route,weighed their impact on the chip's low-power design.Completed the platform activity controller system architecture design,including top-level module,Tick slot timer,interrupt margin timer,GIC interrupt delay,Tick-based interrupt delay timer,Time-based interrupt delay timer,and activation Module.The overall architecture of the module hardware,the operating principle of each part of the state machine,and the hardware register control state machine input signal are analyzed,which realizes the function of Tick generation and interrupt control.By using UVM,AHB communication bus and IP-XACT standardization information,a verification platform for platform activity controller is established,and test cases including basic access function,interrupt delay function,activation function,reset function,register field validity,etc.are written.The verification results show that both code coverage and functional coverage have reached 100%.The power consumption analysis of the platform activity controller and the CPU subsystem is completed,and the dynamic power consumption and static power consumption of the platform activity controller and the CPU subsystem power consumption before and after the platform activity controller is turned on are analyzed.The overall data analysis results show that the dynamic switching power consumption is reduced by 43.8%,the static leakage power consumption is reduced by 18.35%,and the overall power consumption is reduced by 38.04%,achieving the goal of low power design.The design of the platform activity controller has certain practical functions and application value.The final code coverage and function coverage rate are up to 100%.The platform activity controller reduces the total power consumption of the original CPU subsystem by 38.04%.The reliability of the platform activity controller meets the requirements of low power design and has been successfully applied to the entire chip system.The process of designing and verifying the front end of the chip is completed,which solves the problem of high power consumption of the smart chip to a certain extent,and has the significance and value of putting into production practice.