| With the advancement of modern semiconductor technology,products based on microcontrollers such as IoT devices and personal terminal devices have developed rapidly.As the core control unit,the microprocessor’s design requirements have also changed from a single pursuit of effective control to both high performance and low power consumption.Due to the complex working scenarios of modern microprocessor chips,the problems of heat dissipation and battery life are becoming more and more serious.It makes the research on low power consumption of processor chips have important research value.This thesis studies the basic structure and working mode of the processor under the 14nm process.Based on the ARC processor of Synopsys,a power domain management system(Power Domain Management,PDM)is designed to optimize the chip power consumption and reduce the power consumption.The load power consumption of the processor in different scenarios.The processor is divided into multiple power domains for power distribution management,and the system power supply is designed hierarchically through PDM technology.For PDM systems in power consumption scenarios,systems in different power domains can be switched on and off independently.Different subsystem power supply schemes are provided for different working states of the processor,such as HALT mode,normal working mode and power-off mode.In the overall power-on state of the processor,the core and cluster can enter PM1(Power Model)mode or PM2(Power Mode2)mode according to different load requirements.Its cluster shared storage can realize the conversion of working state,power-off state and retention state in different working modes of the cluster.At the same time,each subsystem in the power domain,such as the bus,coherence unit and other systems,can cooperate with the PDM power domain operation to switch the working mode,and realize the corresponding state transition according to the kernel state.Aiming at the difficulty of switching control of the power supply mode of the processor,the thesis designs a state machine to control the core,the cluster and the shared storage of the cluster with low power consumption,and designs the access to the registers in the power transition state,and completes the peripheral control with the processor.The handshake of the device logic.The control structure has a clear hierarchy and has good inheritance and portability.Different subsystem power supply schemes are provided for different working states of the processor,such as HALT mode,normal working mode and power-off mode.In the overall power-on state of the processor,the core and cluster can enter the PM1 mode(Power Model)or the PM2 mode(Power Mode2)according to different load requirements.Its cluster shared storage can realize the conversion of working state,power-off state and retention state in different working modes of the cluster.According to different requirements,each subsystem in the power domain can cooperate with the power domain switch to switch the working mode,and realize the corresponding state transition according to the core working mode.Aiming at the difficulty of switching control of the power supply mode of the processor,the thesis designs a state machine to control the core,the cluster and the shared storage of the cluster with low power consumption,and designs the access to the registers in the power transition state,and completes the peripheral control with the processor.The handshake of the device logic.The control structure has a clear hierarchy and has good inheritance and portability.This thesis completes the verification of the processor power domain system based on the directional functional test of random System Verilog language.A verification platform for processor power domain designs is constructed.Compared with the conventional module-level verification platform,this platform is more sufficient for the verification of complex power supply scenarios in the processor power domain.According to the working characteristics of the components at different levels of the processor,test cases for the corresponding characteristics are designed based on the Perl language.After passing the regression test of a large number of use cases and eliminating the unreachable situation,the final verification coverage rate reaches 100%,which meets the completeness requirement of verification.The analysis of processor power consumption data is completed through the ZeBu prototyping platform.It is confirmed that the processor PDM system can better complete the power-on and power-off control in different scenarios,and the power consumption of the processor low-power mode is reduced by 54.4%compared with the normal working mode.In conclusion,this thesis completes the low-power design and verification of the processor,and designs the corresponding power domain control for different working scenarios of the processor,which effectively reduces the overall power consumption and has important engineering significance. |
