Low power logic design via glitch estimation and power optimization

Low-power consumption has become an important concern for digital designs; this mandates low-power design methodologies and techniques. We first survey low-power full-adder cells and describe simulation experiments that compare them. The experiments include simulating all combinations of input transitions and determine the delay and power consumption for the various full-adder cells. Moreover, the simulation results highlight the weaknesses and the strengths of the various designs and the possible caveats of miscalculations of power consumption of combinational circuits.; We then investigate the main cause of power consumption miss-calculations viz. glitches. Glitches are not functionally significant in synchronous designs, but they consume power. We present a new method to estimate the glitching activity for different circuit nodes. The method is robust and produces accurate glitch probability numbers early in the design cycle. It does not have much overhead and it alleviates existing compute-intensive methods.; We further investigate one of the possible ways to remove glitches from designs, filtering them out using flip-flops. We survey a set of reported flip-flops designed for low power and high performance and highlight the basic features of these flip-flops and evaluate them based on well known metrics. Finally, we conclude with a set of guidelines for both high-performance and low power flip-flop design.; After surveying the set of flip-flops, we delve into more details in flip-flop design and optimization for low power. We introduce a new flip-flop and then compare the lowest power flip-flops surveyed to the new design and conclude that the new flip-flop competes closely to them.; We take the notion of "Transition Density" further and use it in estimating the average dynamic power of CMOS gate designs. We introduce a new method to calculate the dynamic power of different nodes in the ISCAS-85 circuits. We make some circuit modifications to lower the power consumption and show that following a simple set of circuit modifications can significantly lower the power consumption components. We conclude with the importance of establishing an algorithm to cover all possible power optimizations.