Research And Implementation Of A Verification Method For A Low-power WIFI Chip

With the increasing complexity of So C design,nowadays,the power consumption requirements of consumer electronics are getting higher and higher,and low-power technologies in the chip design industry are also emerging in an endless stream.The importance is also getting higher and higher.Take Wi Fi chip as an example.In its design process,the power consumption is mainly reflected in static power and dynamic power.Compared with the previous process,the chip design is actually only concerned.It is dynamic power consumption,but now with the continuous development of the process,especially in the current mainstream process,static power consumption is also very important.From wearable devices to data centers,almost all integrated circuit products have low power consumption as a design focus.This trend has formed a powerful storm in the semiconductor ecosystem.Existing methodologies need to be revised,technology needs to be improved,and expectations need to be adjusted.But even if all aspects are redefined,the problems caused by power consumption will still exist.The main work of this paper is to put forward an efficient and reasonable low-power design scheme through the low-power design and simulation verification of a low-power Wi Fi chip,and build a model for the low-power technology used in the design.An efficient and feasible low-power simulation verification environment.The thesis first studied the power consumption sources in the chip and the current common low-power design technology principles,and then introduced the multiple working modes and power domain divisions of this Wi Fi chip,and explained each power supply in each working mode.Domain switching conditions,low-power design methods used in the design include gated clock technology,gated power technology,multi-threshold voltage technology,multi-power domain technology,etc.,and then use Synopsys' unified power format standard UPF for low power Power consumption design and realization,detailed description of UPF's description of power domain,power network,gated power supply,power state table,level converter,isolation unit,and holding unit.Subsequently,based on the low-power design method used in the chip,a corresponding verification plan was created,including the function point decomposition of verification,test case construction and coverage requirements,etc.;according to the verification plan,a system-level simulation verification environment based on System Verilog was constructed,and The structure of the verification environment and the realization of each component are introduced in detail,the interface interface is designed according to the input and output ports of the design to be tested,the driver is designed according to the excitation required by different test cases,and the function points that need to be verified and monitored The monitor monitor is designed,and the assertion statement is designed using scripts according to the control signal timing of each power domain and the chip IO signal timing,and the function coverage is designed for the main functions that need to be verified.In different low-power operating modes,such as Light Sleep Mode and Deep Sleep Mode,simulations are performed on the power control function of each power domain,the correct use of the isolation unit,and the functions under different power consumption scenarios,verifying the system level The power switch process.The structure of the previous simulation is analyzed in detail from the three aspects of simulation log,simulation waveform and coverage rate,and the results of functional simulation and gate-level simulation are compared from the waveform aspect.The comparison results show that the design function has reached the target and coverage rate.The requirements are basically up to standard.Finally,the PTPX power analysis tool is used to analyze and evaluate the power consumption of the chip at the netlist level to verify that the low power consumption design of the chip achieves the expected effect of greatly reducing power consumption.