Design And Study Of ESD Circuits For Mixed Signal Network Switch Chip

As the application environment is going harsher for IC circuits,the reliability of chips is now an essential issue in design.ESD(Electro-Static Discharge)protection is an important part of Design For Reliability,its implementation requires great efforts and time spending.Especially when the device's gate oxide is much thinner and the break voltage gets lower from deep submicron processes,chips are likely to be failed by ESD.Additionally,with the increasing integration level and more complicated structure in IC circuits,designing a robust and stable ESD protection network for big chips is now indeed a huge challenge.This paper proposed an ascendant ESD protection design for a powerful network switches chip.This chip is based on 0.13 um CMOS process,with operating voltage 3.3V for IO cells and 1.2V in core,including 12 set of internal power supplies.The chip is complex with mix-signal circuits,as well as eight high-speed SerDes interface.This paper firstly introduces related basic theories of ESD design,followed by the studies on Power Clamp circuit design,IO interface ESD protection design,multi-power domain ESD protection and full-chip ESD network architecture.According to the features of this chip,we propose four different Power Clamp circuits.They are applied to high-speed SerDes interface,core circuits and general IO interface circuits.In the design studies of IO interface ESD protection,we use different ESD protection techniques for digital IO and analog IO.All the inputs are equipped by second-stage ESD protection circuit enhancement.In the full-chip ESD network design,we applied the ground as the ESD bus while the bus forms the entire ESD network interconnection in the chip,enabling effective ESD discharge channels between any IO interfaces.The target of this study is physical implementation in engineering.This paper mainly introduces and analysis in circuit designing methodologies and focusing on the study of Power Clamp circuits.The DFM layout of the ESD protection design is briefly described in the final chapter.This chip was taped out,and all the IO interfaces passed the ESD test of 2000 V HBM model,proving the reliability and practicability of the entire ESD protection design.