The Lvds High-speed I / 0 Interface Chip Ftlvds, The Design And Realization

With the great development of the technology of computer architecture and the technology of semiconductor,the frequency of the timing clock in the 1C chips has been faster and faster. Then the difference of data transmission speed between inside and outside of current CMOS chips has been a bottleneck influencing the performance of computer systems.LVDS(Low Voltage Differential Signaling) is an international common interface sdandard that applied to high speed signal transmitter. The high speed LVDS I/O interface cell is an important component of high performance computers and communication electronic equipments,and is helpful to solve this bottleneck problem in the extensive application fields. The high speed LVDS I/O interface chip FTLVDS that we designed in the task is an useful taste to solve the bottleneck.We design the chip FTLVDS by means of "top-down" and "bottom-up" mixed tecknique. The chip's function includes transmitter-receiver of LVDS signal and serializer-deserializer of CMOS digital signal. The full chip can be partitioned to four modules,LVDS driver,LVDS receiver,serializer and deserializer. We implement these modules with different approaches based on their fuctions and characters.The LVDS driver and LVDS receiver designed by the means of full custom design approach,are not only the most important circuits in the chip FTLVDS but also the emphases of the task. The paper has an emphatical discussion on the study and analysis of the circuit structure and layout structure of these two modules,and makes a lot of SPICE simulation and verification.The serializer and deserializer moduls in the FTLVDS chip are designed by the way of standard cell design approach. The paper emphatically discusses the tradeoff and the implementation of several clock synchronization modes and circuit structures,and makes a lot of Verilog simulation and verification on the circuits designed.The whole FTLVDS chip is a combination of LVDS driver,LVDS receiver,serializer and deserializer. It's layout is implemented by the means of full-custom and half-custom mixed design approach,and the chip is taped out.This task of self-determination design of high speed LVDS I/O interface chip,as a part of the project "high speed digital signal interlink and transmit technology" on the foundation of National Laboratory For Parallel & Distributed Processing,on the one hand provide absolutely necessarily experiment foundation and hardware elements for the research of high speed digital signal transmission,on the other hand make an available exploration for the forward design methods of IC chips by means of full-custom and half-custom mixed designapproach.