Research And Design On Pipeline And Register File For Single Event Upset Tolerance

With the progress of semiconductor technology,integrated circuits become smaller and faster.However,at the same time,it has made rediation effects more sensitive.Reduced transistor sizes,higher densities,lower voltages and more aggressive clock frequencies have made them more susceptible to transient faults induced by radiation.Single event upset effect affects the execution of the program by causing erroneous jumps in the program and changing data in the memory(eg,data and program memory and registers),and causes system errors finally.An urgent problem how to reduce the impact of radiation effects on the processor under limited overhead needs to be solved for space applications which require high reliability.In order to find out the areas which susceptible to single event upset in the processor,the Open RISC 1200 processor was chosen to set up the hardware and software platforms.The fault injection tool was used for soft error sensitivity analysis.Based on soft error sensitive areas,the hardware and software reinforcement techniques commonly used by processors are compared.A hardware and software combined reinforcement method,hardware error detection and software error correction,is proposed to fully utilize the advantages of hardware and software.With the reinforcement method proposed in this paper,the pipelines and register stacks which are susceptible to single-event flipping effect in the processor are respectively reinforced.Dual-mode redundant error detection by hardware and pipeline restart error correction by software are uesed for the pipeline.Compared with the traditional three-mode redundancy reinforcement method,the ability to mitigate errors is similar,but the area and power consumption can be reduced by about onethird.The improved two even parity check code is used for the register file.It can effectively corret multi-bit errors.Compared with traditional two-dimensional matrix codes,there are fewer redundant bits and higher code rates when the error correction capability is approximated.Although the error correction time increases,the impact on the system is small with a low flip probability.