Researchs And Designs Of 12bit 100MS/s Hybrid Flash-SAR Analog To Digital Converter

With the rapid development of integrated circuit CMOS technology,analog-to-digital converters have imposed higher requirements on speed,accuracy,and power consumption in order to meet the demand for the rapid development of various types of electronic products.Compared to ADCs with other structures,the features of successive approximation register ADCs are lower power consumption and smaller area.However,a conversion process of an N-bit SAR ADC requires at least N successive comparisons.Moreover,the number of capacitors in a DAC capacitor array is large and increases exponentially with the accuracy of the ADC,thereby limiting the sampling rate of the ADC and the bandwidth of the signal.Therefore,the SAR ADC is suitable for low power,medium and high speed applications.The Flash ADC has the advantages of a simple structure and a particularly high conversion rate.The disadvantage is that as the number of ADC bits increases,the number of comparators increase exponentially with the number of bits,to achieve high precision has a certain degree of limitations.In order to adapt to the rapid development of modern communications applications,the structure of the ADC is also diversified.The hybrid ADC designed in this article combines the high-speed conversion of the Flash ADC and the low power consumption of the SAR ADC.For a single type of ADC,hybrid ADCs can be effectively improved in accuracy,speed,and power consumption.This paper presents a high-capacitance skip/multiplex algorithm for the SAR ADC's low power consumption.Compared with the traditional MCS algorithm,the switching strategy reduces the total capacitance of the capacitor array by half.In order to improve circuit fault tolerance and circuit robustness,a digital calibration algorithm with redundant bits is proposed.This algorithm adds 1 bit of redundant bits to the SAR ADC.When the error caused by the first level of Flash ADC is less than offset voltage,the digital correction circuit in the Level 2 SAR ADC can calibrate the error back and get the correct digital output finally.The 12-bit 100MS/s Flash-SAR hybrid ADC uses a "3+10" two-pole pipeline architecture,is simulated in SMIC 0.18?m CMOS mixed-signal process.When the supply voltage is 1.8V,the sampling frequency is 100 MHz,the signal is a full-scale sine differential signal of 48.145 MHz,the SFDR of the output signal is 95.381 dB,SNDR is 67.923 dB,ENOB is 10.990 bit.When the sampling frequency is 100 MHz and full scale sine differential signal is 1.714 MHz,the SFDR is 97.706 dB,SNDR is 68.766 dB,ENOB is 11.130 bit.