Designs And Researches Of Hybrid A/D Converter Based On Flash-SAR

With the rapid development of CMOS technology, the digital signal processing technology has been greatly improved. Compared with the analog signal, digital signal has higher reliability, simplicity and flexibility, etc., so that digital signal processing has became the mainstream of modern signal processing methods. Analog-to-digital converter (ADC) that is a bridge between analog and digital signals needs to convert analog signals in nature into digital forms firstly and the system then use digital signal processing method to deal with analog signals. So, the demand for ADC is growing,and its research is gaining in popularity. The successive approximation register (SAR)ADC is widely used due to its simple structure, power efficiency and small size characteristics. N-bit SAR ADC with traditional structure requires N comparisons to complete one conversion, and the speed of each comparison is limited by the settling time of the capacitive DAC and the delay of logic control circuit. Therefore, this defect hindered the development of SAR ADC to high-speed and high-resolution field. Flash ADC has high conversion speed due to its simple structure and working principle. Its area and power consumption exponentially grow with the increase in the number of ADC bit. It is a great challenge to design a Flash ADC with high resolution. Flash-SAR ADC is a new ADC structure which combines the advantages of Flash ADC and SAR ADC and has been widely researched due to the perfect trade-off between area, speed,power, and resolution.In this thesis, the principle and system structure of Flash-SAR ADC are introduced firstly. Meanwhile, the non-ideal factors in Flash-SAR ADC are discussed with corresponding solutions. Next, based on analysis and comparison of the existing switching algorithms, a novel algorithm named Higher Capacitor Skipped or Reused(HCSR) is put forward, which greatly improves the dynamic power consumption and chip area of the charge redistribution DAC. Compared with the MCS scheme, the proposed switching scheme reduces the capacitor requirement by almost 50% and improves the average switching energy efficiency by 81.22%. Then, the key blocks of designed ADC are introduced in detail, and the simulation results are shown. Finally, a 10-bit 100MS/s Flash-SAR hybrid ADC is presented in SMIC 0.18?m mixed signal CMOS technology. The proposed ADC is two-stage pipeline ADC with a "3+8"structure, which achieves 10 bit resolution by redundancy digital error correction circuit.The simulation results show that the Flash-SAR ADC achieves 75.879dB SFDR,61.37dB SNDR and 9.902 bit ENOB with Nyquist input frequency at the sampling rate of 100MS/s. When the frequency of input signal is 1.07421875MHz and process corner is FF, the ADC achieves 78.669dB SFDR, 61.839dB SNDR and 9.980 bit ENOB. When process corner is TT, it achieves 76.201dB SFDR, 61.15dB SNDR and 9.865 bit ENOB.When process corner is SS, it achieves 76.937dB SFDR, 60.594dB SNDR and 9.773 bit ENOB. The proposed Flash-SAR ADC consumes 2.41 mW from 1.8V and offers a good energy efficiency of 25.19fJ/conversion-step.