Research On Optimized Gate Replacement Technology For Mitigation NBTI-induced Integrated Circuits Aging

As the integrated circuit manufacturing technology enters nanometer level,the circuit aging problem caused by negative bias temperature instability(NBTI)seriously affects the reliability and stability of integrated circuit.NBTI effect primarily affects the PMOS devices,showing the shift in threshold voltage,resulting in the increase of circuit delay and performance degradation,which will lead to a functional failure in extreme case.Studying and mitigating the influence of NBTI effect on integrated circuit has become one of the important contents of the reliability design.Application of gate replacement(GR)technology to mitigate the NBTI-induce circuit aging needs to locate critical gates at the design stage.However,the negative impact,which affects aging situation of circuit due to the changing of critical gates' output signals,is not considered in the existing research scheme base on gate replacement,resulting in poor optimization result.In this dissertation,an effective measurement method is presented to characterize the NBTI aging degree of gate circuits,and serve as a basis for identifying the circuit critical gate,so as to increase the accuracy and efficiency of critical gate recognition in the optimized gate replacement scheme.Simulation results show that the improvement rate of circuit delay degradation using the proposed scheme is 25.11%,while the average gate replacement rate representing hardware cost is only 5.95%.The proposed scheme improves the anti-aging effect of gate replacement technology with lower hardware overhead.By combining input vector control(IVC)technology with gate replacement technology to mitigate the NBTI-induced circuit aging,the application of GR technology may destroy the optimization results of IVC scheme.In order to improve the compatibility of each scheme and optimize the application of gate replacement technology,according to the anti-aging principles and advantages of each scheme,an optimal input vector selection strategy under the constraint of GR technology is proposed in this dissertation,which further improves the anti-aging capability of our scheme.Simulation results show that our scheme effectively combines the advantages of IVC and GR technology,the improvement rate of circuit delay degradation using our scheme is 33.06%,which is 16.53% higher than the existing scheme.It is verified that our scheme has superior anti-NBTI effect.