Multi-Constraint To Find The Critical Gates Replacement Technology To Relieve The NBTI Effect

With the decrease of device size,negative bias temperature instability is one of the important factors that threaten the reliability of digital circuits.When grid oxide layer of the electric field strength increased,the NBTI effect cause PMOS transistor threshold voltage increases,the time delay of the device also will increase,the delay of the circuit,circuit of aging is aggravating,affect the normal function of the circuit,the circuit could eventually lead to function failure,became an important failure mechanism,so the research on the impact of NBTI effect in the digital logic circuit is imminent.In this dissertation,the influence of NBTI effect on the aging of large scale integrated circuits is studied in this paper,and the problem of circuit aging caused by the NBTI effect is studied,and the corresponding solutions are proposed.Based on the traditional NBTI static timing analysis framework,we first introduced the gate replacement process framework for identifying key gates under multi-constraints.Then we introduced in detail how multi-constraint conditions are calculated: how to calculate the influence factors of critical gates under path constraints,and how Calculate the critical gate influence factor and consider the influence factor of the critical gate under the protective constraint of the gate entry type non-gate type.The larger the influence factor of the critical gate,the more the influence of the protection of the gate on the circuit is,the more three kinds of constraints are adopted.The next intersection is the collection of precise critical gates,and finally the gate replacement is performed for the critical gate.The experiment proves the correctness and validity of the multi-constraint method proposed in this paper.When the timing margin is 5%,the number of identifications of key gates is reduced by an average of 21.37% relative to the literature,and is reduced by an average of 21.16% compared to the literature.The aging delay caused by the NBTI effect After 10 years of work,the average time delay improvement rate for this paper is 11.13%,for the literature,the relative average increase is 12.08%,for the literature,the average increase is 25.20%,proving that our method is on the critical gates.The positioning and recognition are not only less but also more accurate,and the improvement in time delay for protection is obviously better.According to the replacement of the gate will inevitably bring about the inevitable additional delay overhead.On the one hand,this article wants to reduce the aging delay caused by gate replacement,and on the other hand,it wants to minimize the impact of the delay introduced by the gate replacement on the circuit.Considering the above two considerations,we propose a streamlined improvement program to determine whether the critical gate is worthy of protection against the identified critical gate,or whether the critical gate entry needs to be replaced if the critical gate is used as a fan.On non-critical paths,we replace;if we are on non-critical paths,we avoid introducing more delay increments and give up protection.From the experiments to verify the scheme of this paper,the delay improvement rate of the non-simplified scheme is compared with that of the reduced scheme in this paper.The relative average improvement is 7.23%..On the replacement rate,the replacement rate of 13.37% is reduced by 13.45% compared with the average of the reduced scheme in this dissertation.