Research On Aging And Built-in Self-test Of VLSI

With the development of VLSI technology, integration and complexity of circuit continue toimprove. Circuit aging becomes the bottleneck of the circuit reliability and performance. Testingand reliability of the circuit is facing serious challenges. Aging and BIST are researched in thisthesis. BIST is researched to achieve high test data compression ratio, short test application timeand low test power. NBTI-induced circuit aging is researched to predict aging in the design phase.Furthermore, reusing BIST to mitigate aging is researched. The major contributions of thisdissertation include:1. A BIST scheme is proposed for multiple scan chains based on the theory of foldingcomputing. Firstly, the test pattern set is horizontally compressed by the input reduction techniquewhich can identifies compatible scan chains; the compatible scan chains are designed to broadcasttest data during testing. Secondly, the test pattern set is vertically compressed into the seed setaccording to folding computing theory; and so adjoining test vectors of the same folding seed onlydiffer in one bit position and shift into multiple scan chains in parallel during testing. For paralleltesting, only a simple test control circuit can effectively reduce the average shift power, testapplication time and achieve higher test data compression rate. Experiment results with ISCASbenchmark circuit demonstrate the average test compression rate of the proposed scheme is95.07%,and the average test application time is13.35%of the similar scheme.2. Selection sequence of parallel folding counter is produced. Selection test sequences aregenerated by recording group sequence number and in-group sequence number which denotefolding index based on analysis of parallel folding computing theory, where it avoid generatinguseless and redundant test sequences. So it can greatly reduce the test application time and achievehigh test compression rate. Experiment results on ISCAS benchmark circuits demonstrate theaverage test compression rate of the proposed scheme is94.48%, and the average test applicationtime is15.31%of the previous scheme.3. An approach of identifying critical gates under circuit aging considering pathcorrelation is provided. A NBTI-aware timing analysis framework is based on a simplified NBTIgate-level aging model. It determines aging-sensitive potential critical path set in circuit and thenfurther determines aging-sensitive critical gates considering path correlation. It implements easily.Experiment results with ISCAS benchmark circuit at65nm technology, compared to similarscheme, demonstrate the proposed method can determine fewer critical gates more accurately andreduce cost of anti-aging design under the premise of protecting circuit to meet the same timingrequirement after ten-year NBTI effect. 4. A technique of applying input vector constraint gate replacement by reusing BISTcircuit during the standby time is proposed. Firstly, potential critical paths are found by usingdynamic and static NBTI-aware static timing analysis. Then critical gates are found by consideringpath correlation. Secondly, input vector is generated with the maximum extent of the critical gatesin the recovery phase. Finally, gate replacement is applied to the critical gates beyond control.Experiment results with ISCAS benchmark circuit demonstrate the average gate replacement rate isreduced to9.68%, and the average delay improvement is increased to39.65%with the circuittiming margin5%.