Research On Aging Of VLSI Induced By NBTI

AS VLSI nanometer technology scales, the performance of circuits has been largely improved. Nevertheless, the integration level and the complexity of circuits have increased correspondingly, the circuit aging problems resulting from which have become a key bottleneck of the circuit reliability and performance, and have brought serious challenges to circuits reliability research. For 45nm technology, negative bias temperature instability (NBTI) effect is the primary factor which limits circuit reliability and performance.In this thesis, the influence that NBTI has on VLSI is researched intensively. After a research of the circuits aging problems caused by NBTI effect, the corresponding solutions are proposed. The main work is as follows:To begin with, the basic knowledge and concepts of circuit aging are briefly described, the factors causing the circuit aging are classified and the primary factor-NBTI effect causing circuits aging problems under the nanometer process is introduced and researched. The illustration of self-recovery mechanisms and models of NBTI effect are highlighted, the circuit aging prediction and protection technologies solving the circuit aging problems caused by NBTI effect are classified, and the advantages and disadvantages of each technique are analyzed and compared.What’s more, based on self-recovery mechanisms of NBTI effect, an efficient method to mitigate NBTI-induced circuit degradation by gate replacement technique is provided. In this thesis, a design flow framework and a gate replacement algorithm based on the gate replacement technique are proposed. The gate replacement technique not only effectively solves the problem which input vector control (IVC) technique not applying to larger circuits, but also keeps the original gate structure without introducing extra stacking effect, compared with similar internal node control (INC) technique.Finally, the area, the repalcement and the improvement ratio are validated through a series of experiments and the results are compared with some similar techniques. Experimental results based on the ISCAS85 benchmark circuits and 45nm transistor model relational parameter show that, when compared with the similar techniques, the proposed gate replacement technique mitigates averagely 9.11% of circuit aging.